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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-02 23:29:07 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-10-05 13:21:55 +0000
commitf9891c8b469232cca28f0b12f613274f127748df (patch)
treeb10131ca552bcce69e92490a5f4a76575405387a /src/northbridge/intel/i945
parentad787e18e0ed24495132d0e9e638ed835afad354 (diff)
downloadcoreboot-f9891c8b469232cca28f0b12f613274f127748df.tar.xz
kontron/986lcd-m,roda/rk886ex: Drop secondary PCI reset
The extra PCI bus RST# and 200ms delay there was workaround for custom add-on hardware. Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/i945')
-rw-r--r--src/northbridge/intel/i945/early_init.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 7ed58f67ab..ee10fdccb6 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -17,7 +17,6 @@
#include <cf9_reset.h>
#include <console/console.h>
#include <arch/io.h>
-#include <delay.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
@@ -869,14 +868,6 @@ static void ich7_setup_pci_express(void)
pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
}
-void ich7_p2p_secondary_reset(void)
-{
- pci_devfn_t p2p_bridge = PCI_DEV(0, 0x1e, 0);
- pci_s_assert_secondary_reset(p2p_bridge);
- mdelay(200);
- pci_s_deassert_secondary_reset(p2p_bridge);
-}
-
void i945_early_initialization(void)
{
/* Print some chipset specific information */