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| author | Stefan Reinauer <stepan@coresystems.de> | 2009-03-06 19:11:52 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-03-06 19:11:52 +0000 |
| commit | 43b29cf891c78a2cd01d22a2731c7da828d79e0a (patch) | |
| tree | 8f1b3eaba031a92dbc4a128a4ddd2c81cf6a552d /src/northbridge/intel/i945 | |
| parent | ae762b5d3b84b2b6f8cf80195d10e9544605aa4a (diff) | |
| download | coreboot-43b29cf891c78a2cd01d22a2731c7da828d79e0a.tar.xz | |
Fix mmconf (PCIe memory mapped config space access) support in v2. It was
horribly broken and thus never used by any platform. This needs to get
straightened out so current chipsets drivers can use the full feature set.
Create wrapper functions similar to the io pci config space ones.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i945')
| -rw-r--r-- | src/northbridge/intel/i945/northbridge.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 9cb5cefe62..ad1d938710 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2007-2009 coresystems GmbH * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -199,7 +199,11 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ +#if MMCONF_SUPPORT_DEFAULT + .ops_pci_bus = &pci_ops_mmconf, +#else + .ops_pci_bus = &pci_cf8_conf1, +#endif }; static void mc_read_resources(device_t dev) |