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| author | Patrick Georgi <pgeorgi@chromium.org> | 2015-07-13 19:24:07 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-09 10:20:43 +0000 |
| commit | 771328f7dff554fe06a2dc931097b0e129e2113f (patch) | |
| tree | e433acb69fbc2667e72d02b628f3cda073f73b59 /src/northbridge/intel/i945 | |
| parent | 05b7cab1d7042d82e98387d6fc5849ff2d4df9db (diff) | |
| download | coreboot-771328f7dff554fe06a2dc931097b0e129e2113f.tar.xz | |
intel/i945: add timestamps in romstage
It is able to do so if timestamps are initialized.
Change-Id: Ic95313a19646b66dc1633fb680e54bfc61ec90be
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945')
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index c259530338..71d98538da 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -29,6 +29,7 @@ #include "chip.h" #include <cbmem.h> #include <device/dram/ddr2.h> +#include <timestamp.h> /* Debugging macros. */ #if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) @@ -2735,6 +2736,7 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) struct sys_info sysinfo; u8 reg8; + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); memset(&sysinfo, 0, sizeof(sysinfo)); @@ -2836,4 +2838,5 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) printk(BIOS_DEBUG, "RAM initialization finished.\n"); sdram_setup_processor_side(); + timestamp_add_now(TS_AFTER_INITRAM); } |