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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-12-08 11:34:24 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-10 11:16:07 +0000 |
| commit | 13746076e95a611b56dfe37519685ae125172bb4 (patch) | |
| tree | 3d41161b459454cfc89db62c9412e07f3ed1e8a0 /src/northbridge/intel/i945 | |
| parent | e86ded841fdb3846b070a9cbe1793f72efe540aa (diff) | |
| download | coreboot-13746076e95a611b56dfe37519685ae125172bb4.tar.xz | |
mainboard/(i945,ich7): Remove commented RCBA32(0x341c) code
PCIe root port clock gate is already enabled at i945/early_init.c
Also fix comments when only PCIe root port is enabled.
Change-Id: Ica38529dbdd5cc51b19b426999a1d9f0b678b4f5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37576
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 13dce61325..6629a0e0f8 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -837,6 +837,7 @@ static void ich7_setup_root_complex_topology(void) static void ich7_setup_pci_express(void) { + /* Enable PCIe Root Port Clock Gate */ RCBA32(CG) |= (1 << 0); /* Initialize slot power limit for root ports */ |