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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 18:37:32 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:32:20 +0000 |
| commit | 9addda3c410041ea93ae5587d17460da9a9c312f (patch) | |
| tree | 5579f274b2d7e801b819d5711ddbdf96414101c0 /src/northbridge/intel/ironlake/early_init.c | |
| parent | c642a0d8942735b393040b877769f1d4a3a9ebe8 (diff) | |
| download | coreboot-9addda3c410041ea93ae5587d17460da9a9c312f.tar.xz | |
nb/intel/ironlake: Add Generic Non-Core register definitions
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/ironlake/early_init.c')
| -rw-r--r-- | src/northbridge/intel/ironlake/early_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index 24657d6616..fa89bd9e45 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -43,7 +43,7 @@ static void early_cpu_init(void) /* bit 0 = disable multicore, bit 1 = disable quadcore, bit 8 = disable hyperthreading. */ - pci_update_config32(QPI_NON_CORE, 0x80, 0xfffffefc, 0x10000); + pci_update_config32(QPI_NON_CORE, DESIRED_CORES, 0xfffffefc, 0x10000); u8 reg8; struct cpuid_result result; |