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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 17:30:49 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:31:22 +0000 |
| commit | 93d9517795b58fca2639bc66e359a61219e82b81 (patch) | |
| tree | 2562d8496997da412d14cd1ab807965a2eb3389c /src/northbridge/intel/ironlake/ironlake.h | |
| parent | 67573371d5ade1ad388316585901ee9d0edfe512 (diff) | |
| download | coreboot-93d9517795b58fca2639bc66e359a61219e82b81.tar.xz | |
nb/intel/ironlake: Add definition for QPI Link PCI device
On multi-socket platforms, there can be two QPI buses, each with its own
PCI device. We only have one QPI link on Arrandale, though. In case
support for multi-socket processors ever gets added, name it Link 0.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/ironlake/ironlake.h')
| -rw-r--r-- | src/northbridge/intel/ironlake/ironlake.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index fa59565ba8..bd42f21006 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -60,6 +60,11 @@ #define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */ #define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */ +/* + * QPI Link 0 + */ +#define QPI_LINK_0 PCI_DEV(QUICKPATH_BUS, 2, 0) + /* Device 0:2.0 PCI configuration space (Graphics Device) */ |