diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 17:30:49 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:31:22 +0000 |
commit | 93d9517795b58fca2639bc66e359a61219e82b81 (patch) | |
tree | 2562d8496997da412d14cd1ab807965a2eb3389c /src/northbridge/intel/ironlake/raminit.c | |
parent | 67573371d5ade1ad388316585901ee9d0edfe512 (diff) | |
download | coreboot-93d9517795b58fca2639bc66e359a61219e82b81.tar.xz |
nb/intel/ironlake: Add definition for QPI Link PCI device
On multi-socket platforms, there can be two QPI buses, each with its own
PCI device. We only have one QPI link on Arrandale, though. In case
support for multi-socket processors ever gets added, name it Link 0.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/ironlake/raminit.c')
-rw-r--r-- | src/northbridge/intel/ironlake/raminit.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index f8f6b74466..2c475694d4 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3950,11 +3950,11 @@ void raminit(const int s3resume, const u8 *spd_addrmap) MCHBAR8_OR(0x2ca8, 1); // guess } - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x048); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 0), 0x048, 0x140000); - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! - pci_write_config32(PCI_DEV(0xff, 2, 0), 0x058, 0x64555); - pci_read_config32(PCI_DEV(0xff, 2, 0), 0x058); // !!!! + pci_read_config32(QPI_LINK_0, 0x048); // !!!! + pci_write_config32(QPI_LINK_0, 0x048, 0x140000); + pci_read_config32(QPI_LINK_0, 0x058); // !!!! + pci_write_config32(QPI_LINK_0, 0x058, 0x64555); + pci_read_config32(QPI_LINK_0, 0x058); // !!!! pci_read_config32(PCI_DEV (0xff, 0, 0), 0xd0); // !!!! pci_write_config32(PCI_DEV (0xff, 0, 0), 0xd0, 0x180); gav(MCHBAR32(0x1af0)); // !!!! |