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author | Patrick Rudolph <siro@das-labor.org> | 2016-06-09 18:13:34 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2016-06-12 12:48:44 +0200 |
commit | 266a1f794dc28053e97794cbeb3f1a588137698b (patch) | |
tree | 7cb11796fa351bd50d15af6be9508a15be223192 /src/northbridge/intel/nehalem/chip.h | |
parent | e7f35cd2924de7c9b2e8a74a50d35928b9da76a4 (diff) | |
download | coreboot-266a1f794dc28053e97794cbeb3f1a588137698b.tar.xz |
nb/intel/raminit (native): Read PCI mmio size from devicetree
Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.
Tested on Sandybridge Lenovo T520.
Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/nehalem/chip.h')
-rw-r--r-- | src/northbridge/intel/nehalem/chip.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index caf98196bd..a9d136baad 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -41,6 +41,11 @@ struct northbridge_intel_nehalem_config { u32 gpu_pch_backlight; /* PCH Backlight PWM value */ struct i915_gpu_controller_info gfx; + + /* + * Maximum PCI mmio size in MiB. + */ + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */ |