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author | Vladimir Serbinenko <phcoder@gmail.com> | 2015-05-29 16:52:50 +0200 |
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committer | Vladimir Serbinenko <phcoder@gmail.com> | 2015-06-10 05:34:01 +0200 |
commit | 0f9aa1c9cd49d6c3f8545ce50bbeb79feb7f615b (patch) | |
tree | 0904c509a5f0708ef4a0e3a70d5639c35ade0d6a /src/northbridge/intel/nehalem/northbridge.c | |
parent | bbd2647b388320b10ae836f65b3d35754113dc02 (diff) | |
download | coreboot-0f9aa1c9cd49d6c3f8545ce50bbeb79feb7f615b.tar.xz |
model_2065x: Use common i945-ivy TSEG SMM init.
Change-Id: I0302cbaeb45a55a4cfee94692eb7372f2b6b206d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10468
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel/nehalem/northbridge.c')
-rw-r--r-- | src/northbridge/intel/nehalem/northbridge.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 43bd846b92..a3c2eeaa11 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -37,6 +37,7 @@ #include <cbmem.h> #include "chip.h" #include "nehalem.h" +#include <cpu/intel/smm/gen1/smi.h> static int bridge_revision_id = -1; @@ -165,6 +166,18 @@ static void mc_read_resources(device_t dev) add_fixed_resources(dev, 10); } +void +northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size) +{ + device_t dev; + u32 bgsm; + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + *tsegmb = pci_read_config32(dev, TSEG) & ~1; + bgsm = pci_read_config32(dev, D0F0_GTT_BASE); + *tseg_size = bgsm - *tsegmb; +} + static void mc_set_resources(device_t dev) { /* And call the normal set_resources */ |