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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-10 15:50:04 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2019-10-13 12:46:18 +0000 |
commit | 2882253237f254d5f78b7531ef3cefb974cd4bbb (patch) | |
tree | 91216e1814cff2806f15c503155d3ad3446cc48e /src/northbridge/intel/nehalem/romstage.c | |
parent | b9c9cd75e71edf2fb9b34c451e7ad74a5200de1d (diff) | |
download | coreboot-2882253237f254d5f78b7531ef3cefb974cd4bbb.tar.xz |
nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK
A few notable changes:
- Microcode init is done in assembly during the CAR init.
- The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size
against which the romstage stack guards protected.
- The romstage mainboard_lpc_init() hook is removed in favor of the
existing bootblock_mainboard_early_init().
Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/nehalem/romstage.c')
-rw-r--r-- | src/northbridge/intel/nehalem/romstage.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c index 54766de0e7..8188303877 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/nehalem/romstage.c @@ -45,11 +45,6 @@ void mainboard_romstage_entry(void) /* TODO, make this configurable */ nehalem_early_initialization(NEHALEM_MOBILE); - pch_pre_console_init(); - - /* Initialize console device(s) */ - console_init(); - early_pch_init(); /* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */ |