summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/nehalem
diff options
context:
space:
mode:
authorVladimir Serbinenko <phcoder@gmail.com>2014-08-03 14:51:00 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2014-08-03 15:47:00 +0200
commit55391c422f8c45e40bb014d238769501aed65d56 (patch)
treece880400282f0e850a937a8258adaa2c311b0d97 /src/northbridge/intel/nehalem
parent63e1948643fcbd763c83b6baa6cd9a077d49f1fc (diff)
downloadcoreboot-55391c422f8c45e40bb014d238769501aed65d56.tar.xz
nehalem: Make UMA size configurable in CMOS.
All modes tested on X201. Change-Id: I23df81523196ea3f5fdb10eb04f4496c00aaeb9f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/northbridge/intel/nehalem')
-rw-r--r--src/northbridge/intel/nehalem/raminit.c20
1 files changed, 11 insertions, 9 deletions
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index b1356c21b2..74ddb4b3ff 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -3796,6 +3796,8 @@ static void dmi_setup(void)
void chipset_init(const int s3resume)
{
u8 x2ca8;
+ u16 ggc;
+ u8 gfxsize;
x2ca8 = read_mchbar8(0x2ca8);
if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) {
@@ -3825,13 +3827,15 @@ void chipset_init(const int s3resume)
write_mchbar16(0x1170, 0xb880);
read_mchbar8(0x1210);
write_mchbar8(0x1210, 0x84);
- pcie_read_config8(NORTHBRIDGE, D0F0_GGC); // = 0x52
- pcie_write_config8(NORTHBRIDGE, D0F0_GGC, 0x2);
- pcie_read_config8(NORTHBRIDGE, D0F0_GGC); // = 0x2
- pcie_write_config8(NORTHBRIDGE, D0F0_GGC, 0x52);
- pcie_read_config16(NORTHBRIDGE, D0F0_GGC); // = 0xb52
- pcie_write_config16(NORTHBRIDGE, D0F0_GGC, 0xb52);
+ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) {
+ /* 0 for 32MB */
+ gfxsize = 0;
+ }
+
+ ggc = 0xb00 | ((gfxsize + 5) << 4);
+
+ pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2);
u16 deven;
deven = pcie_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3
@@ -3854,9 +3858,7 @@ void chipset_init(const int s3resume)
read_mchbar32(0x30);
write_mchbar32(0x30, 0x40);
- pcie_read_config8(SOUTHBRIDGE, 0x8); // = 0x6
- pcie_read_config16(NORTHBRIDGE, D0F0_GGC); // = 0xb52
- pcie_write_config16(NORTHBRIDGE, D0F0_GGC, 0xb50);
+ pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc);
gav(read32(DEFAULT_RCBA | 0x3428));
write32(DEFAULT_RCBA | 0x3428, 0x1d);
}