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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-02 08:56:05 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-12-07 13:00:56 +0100
commite25b5ef39fd10e48e87e0c4770a721a786e36a36 (patch)
tree113c2b4eba9bf7fddd6badbafc3c0f6ac0cef04f /src/northbridge/intel/nehalem
parent3d15e10aef5811e8c7146e5defb0e36b848547ed (diff)
downloadcoreboot-e25b5ef39fd10e48e87e0c4770a721a786e36a36.tar.xz
MMCONF_SUPPORT: Consolidate resource registration
Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17695 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/nehalem')
-rw-r--r--src/northbridge/intel/nehalem/Kconfig4
-rw-r--r--src/northbridge/intel/nehalem/northbridge.c11
2 files changed, 6 insertions, 9 deletions
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 4dada50aaf..884660ad88 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -24,6 +24,10 @@ config NORTHBRIDGE_INTEL_NEHALEM
if NORTHBRIDGE_INTEL_NEHALEM
+config MMCONF_BUS_NUMBER
+ int
+ default 256
+
config CBFS_SIZE
hex
default 0x100000
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 06c0a9655b..779e49cd54 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -69,11 +69,6 @@ static void add_fixed_resources(struct device *dev, int index)
0xfed1c000-0xfed20000 RCBA
0xfed90000-0xfed94000 IOMMU
0xff800000-0xffffffff ROM. */
- resource = new_resource(dev, index++);
- resource->base = (resource_t) 0xe0000000;
- resource->size = (resource_t) 0x10000000;
- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
resource = new_resource(dev, index++);
resource->base = (resource_t) 0xfed00000;
@@ -98,10 +93,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
}
- /* TODO We could determine how many PCIe busses we need in
- * the bar. For now that number is hardcoded to a max of 64.
- * See e7525/northbridge.c for an example.
- */
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
@@ -119,6 +110,8 @@ static void mc_read_resources(device_t dev)
pci_dev_read_resources(dev);
+ mmconf_resource(dev, 0x50);
+
tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)),
D0F0_TOUUD);