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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-22 22:52:14 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-04-09 12:03:58 +0000 |
| commit | 2c3fd499cf0672a8da669e40be84112a02b5a77c (patch) | |
| tree | c2caa870a8923a4a87bfd3507029b0ddf6484114 /src/northbridge/intel/nehalem | |
| parent | d538dd1fe70a333c929a2eb7c4106608bcd05257 (diff) | |
| download | coreboot-2c3fd499cf0672a8da669e40be84112a02b5a77c.tar.xz | |
intel/nehalem post-car: Use postcar_frame for MTRR setup
Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE
and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions
are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM.
Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/nehalem')
| -rw-r--r-- | src/northbridge/intel/nehalem/Kconfig | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/ram_calc.c | 35 |
2 files changed, 35 insertions, 2 deletions
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 4fdd2bd282..6a9d0debad 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -20,8 +20,8 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_EDID select TSC_MONOTONIC_TIMER select INTEL_GMA_ACPI + select RELOCATABLE_RAMSTAGE select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE - select ACPI_HUGE_LOWMEM_BACKUP select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index 4d73ee9fc2..37c1ed3420 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2012 ChromeOS Authors * Copyright (C) 2013 Vladimir Serbinenko. * * This program is free software; you can redistribute it and/or modify @@ -15,9 +16,13 @@ #define __SIMPLE_DEVICE__ +#include <arch/cpu.h> #include <arch/io.h> #include <cbmem.h> +#include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/x86/mtrr.h> +#include <program_loading.h> #include "nehalem.h" static uintptr_t smm_region_start(void) @@ -32,7 +37,35 @@ void *cbmem_top(void) return (void *) smm_region_start(); } +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) { - return (void*)CONFIG_RAMTOP; + struct postcar_frame pcf; + uintptr_t top_of_ram; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); } |