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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-14 18:18:46 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-17 15:01:38 +0000 |
| commit | b572c9d5e553c0cefc9d2f43c924430324a6eaaf (patch) | |
| tree | 237b1538216a4917a8fd53c22d7bdbfc01f4ca8f /src/northbridge/intel/nehalem | |
| parent | c892db63982cf7bdd0979812b03e268137be0a4e (diff) | |
| download | coreboot-b572c9d5e553c0cefc9d2f43c924430324a6eaaf.tar.xz | |
nb/intel/nehalem: Add some debug output
Change-Id: Icbdada0a8cdbcface5124a5f9ebd3d667c376902
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/nehalem')
| -rw-r--r-- | src/northbridge/intel/nehalem/raminit.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 75be57231b..46189117a7 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3730,6 +3730,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap) int cbmem_wasnot_inited; x2ca8 = MCHBAR8(0x2ca8); + + printk(RAM_DEBUG, "Scratchpad MCHBAR8(0x2ca8): 0x%04x\n", x2ca8); + deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); memset(&info, 0x5a, sizeof(info)); @@ -4241,6 +4244,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) if (x2ca8 == 0) { MCHBAR8_AND(0x2ca8, ~3); MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"? + /* This issues a CPU reset without resetting the platform */ + printk(BIOS_DEBUG, "Issuing a CPU reset\n"); MCHBAR32_OR(0x1af0, 0x10); halt(); } |