x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

5 files changed, 105 insertions, 90 deletions

diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
index 460942f121..4a208ce5e1 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -120,7 +120,7 @@ static int init_opregion_vbt(igd_opregion_t * opregion)
 	optionrom_header_t *oprom = (optionrom_header_t *) vbios;
 	optionrom_vbt_t *vbt = (optionrom_vbt_t *) (vbios + oprom->vbt_offset);
 
-	if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+	if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
 		printk(BIOS_DEBUG, "VBT not found!\n");
 		return 1;
 	}
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index ee8c17a18c..56c0d68724 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -36,7 +36,7 @@ static void nehalem_setup_bars(void)
 {
 	/* Setting up Southbridge. In the northbridge code. */
 	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
 
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
 	/* Enable ACPI BAR */
@@ -59,13 +59,13 @@ static void nehalem_setup_bars(void)
 	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
 	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4,
 			   (0LL + DEFAULT_EPBAR) >> 32);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
 	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4,
-			   (0LL + DEFAULT_MCHBAR) >> 32);
+			   (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32);
 
-	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
 	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4,
-			   (0LL + DEFAULT_DMIBAR) >> 32);
+			   (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32);
 
 	/* Set C0000-FFFFF to access RAM on both reads and writes */
 	pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30);
@@ -163,7 +163,7 @@ void nehalem_early_initialization(int chipset_type)
 
 	early_cpu_init();
 
-	pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR);
+	pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR);
 	pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
 			   PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index c3e2a492cf..9fc4bd45ba 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -274,12 +274,12 @@ static struct resource *gtt_res = NULL;
 
 u32 gtt_read(u32 reg)
 {
-	return read32(gtt_res->base + reg);
+	return read32(res2mmio(gtt_res, reg, 0));
 }
 
 void gtt_write(u32 reg, u32 data)
 {
-	write32(gtt_res->base + reg, data);
+	write32(res2mmio(gtt_res, reg, 0), data);
 }
 
 static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
@@ -561,7 +561,7 @@ static void gma_pm_init_post_vbios(struct device *dev)
 
 #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
 
-static void train_link(u32 mmio)
+static void train_link(u8 *mmio)
 {
 	/* Clear interrupts. */
 	write32(mmio + DEIIR, 0xffffffff);
@@ -584,7 +584,7 @@ static void train_link(u32 mmio)
 	read32(mmio + 0x000f0014); // = 0x00000600
 }
 
-static void power_port(u32 mmio)
+static void power_port(u8 *mmio)
 {
 	read32(mmio + 0x000e1100); // = 0x00000000
 	write32(mmio + 0x000e1100, 0x00000000);
@@ -639,7 +639,7 @@ static void power_port(u32 mmio)
 }
 
 static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
-			   u32 mmio, u32 physbase, u16 piobase, u32 lfb)
+			   u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
 {
 	int i;
 	u8 edid_data[128];
@@ -1020,8 +1020,8 @@ static void gma_func0_init(struct device *dev)
 	    && lfb_res && lfb_res->base) {
 		printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n",
 		       gtt_res->base);
-		intel_gma_init(conf, gtt_res->base, physbase, pio_res->base,
-			       lfb_res->base);
+		intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
+			       pio_res->base, lfb_res->base);
 	}
 
 	/* Linux relies on VBT for panel info.  */
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 73137b21e7..b90e5a910d 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -186,7 +186,7 @@ enum {
 					(could be reduced to 10 bytes) */
 
 
-#define DEFAULT_HECIBAR		0xfed17000
+#define DEFAULT_HECIBAR		((u8 *)0xfed17000)
 
 				/* 4 KB per PCIe device */
 #define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS
@@ -454,10 +454,15 @@ void init_iommu(void);
 
 /* Northbridge BARs */
 #define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS	/* 4 KB per PCIe device */
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR		((u8 *)0xfed10000)	/* 16 KB */
+#define DEFAULT_DMIBAR		((u8 *)0xfed18000)	/* 4 KB */
+#else
 #define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
 #define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
+#endif
 #define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
-#define DEFAULT_RCBABASE	0xfed1c000
+#define DEFAULT_RCBABASE	((u8 *)0xfed1c000)
 
 #define QUICKPATH_BUS 0xff
 
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 85c82c9e9e..3917288e59 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -200,6 +200,16 @@ static u16 read_1d0(u16 addr, int split)
 	return val;
 }
 
+static void write32p(uintptr_t addr, uint32_t val)
+{
+	write32((void *)addr, val);
+}
+
+static uint32_t read32p(uintptr_t addr)
+{
+	return read32((void *)addr);
+}
+
 static void sfence(void)
 {
 #if REAL
@@ -314,36 +324,36 @@ static int rw_test(int rank)
 	int ok = 0xff;
 	int i;
 	for (i = 0; i < 64; i++)
-		write32((rank << 28) | (i << 2), 0);
+		write32p((rank << 28) | (i << 2), 0);
 	sfence();
 	for (i = 0; i < 64; i++)
-		gav(read32((rank << 28) | (i << 2)));
+		gav(read32p((rank << 28) | (i << 2)));
 	sfence();
 	for (i = 0; i < 32; i++) {
 		u32 pat = (((mask >> i) & 1) ? 0xffffffff : 0);
-		write32((rank << 28) | (i << 3), pat);
-		write32((rank << 28) | (i << 3) | 4, pat);
+		write32p((rank << 28) | (i << 3), pat);
+		write32p((rank << 28) | (i << 3) | 4, pat);
 	}
 	sfence();
 	for (i = 0; i < 32; i++) {
 		u8 pat = (((mask >> i) & 1) ? 0xff : 0);
 		int j;
 		u32 val;
-		gav(val = read32((rank << 28) | (i << 3)));
+		gav(val = read32p((rank << 28) | (i << 3)));
 		for (j = 0; j < 4; j++)
 			if (((val >> (j * 8)) & 0xff) != pat)
 				ok &= ~(1 << j);
-		gav(val = read32((rank << 28) | (i << 3) | 4));
+		gav(val = read32p((rank << 28) | (i << 3) | 4));
 		for (j = 0; j < 4; j++)
 			if (((val >> (j * 8)) & 0xff) != pat)
 				ok &= ~(16 << j);
 	}
 	sfence();
 	for (i = 0; i < 64; i++)
-		write32((rank << 28) | (i << 2), 0);
+		write32p((rank << 28) | (i << 2), 0);
 	sfence();
 	for (i = 0; i < 64; i++)
-		gav(read32((rank << 28) | (i << 2)));
+		gav(read32p((rank << 28) | (i << 2)));
 
 	return ok;
 }
@@ -1072,12 +1082,12 @@ static void jedec_read(struct raminfo *info,
 		    (value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8)
 								<< 1);
 
-	read32((value << 3) | (total_rank << 28));
+	read32p((value << 3) | (total_rank << 28));
 
 	write_mchbar8(0x271, (read_mchbar8(0x271) & 0xC3) | 2);
 	write_mchbar8(0x671, (read_mchbar8(0x671) & 0xC3) | 2);
 
-	read32(total_rank << 28);
+	read32p(total_rank << 28);
 }
 
 enum {
@@ -1562,7 +1572,7 @@ static void collect_system_info(struct raminfo *info)
 	unsigned channel;
 
 	/* Wait for some bit, maybe TXT clear. */
-	while (!(read8(0xfed40000) & (1 << 7))) ;
+	while (!(read8((u8 *)0xfed40000) & (1 << 7))) ;
 
 	if (!info->heci_bar)
 		gav(info->heci_bar =
@@ -1746,9 +1756,9 @@ static const struct ram_training *get_cached_training(void)
 /* FIXME: add timeout.  */
 static void wait_heci_ready(void)
 {
-	while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ;	// = 0x8000000c
-	write32((DEFAULT_HECIBAR | 0x4),
-		(read32(DEFAULT_HECIBAR | 0x4) & ~0x10) | 0xc);
+	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ;	// = 0x8000000c
+	write32((DEFAULT_HECIBAR + 0x4),
+		(read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
 }
 
 /* FIXME: add timeout.  */
@@ -1759,10 +1769,10 @@ static void wait_heci_cb_avail(int len)
 		u32 raw;
 	} csr;
 
-	while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ;
+	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ;
 
 	do
-		csr.raw = read32(DEFAULT_HECIBAR | 0x4);
+		csr.raw = read32(DEFAULT_HECIBAR + 0x4);
 	while (len >
 	       csr.csr.buffer_depth - (csr.csr.buffer_write_ptr -
 				       csr.csr.buffer_read_ptr));
@@ -1776,12 +1786,12 @@ static void send_heci_packet(struct mei_header *head, u32 * payload)
 	wait_heci_cb_avail(len + 1);
 
 	/* FIXME: handle leftovers correctly.  */
-	write32(DEFAULT_HECIBAR | 0, *(u32 *) head);
+	write32(DEFAULT_HECIBAR + 0, *(u32 *) head);
 	for (i = 0; i < len - 1; i++)
-		write32(DEFAULT_HECIBAR | 0, payload[i]);
+		write32(DEFAULT_HECIBAR + 0, payload[i]);
 
-	write32(DEFAULT_HECIBAR | 0, payload[i] & ((1 << (8 * len)) - 1));
-	write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 0x4);
+	write32(DEFAULT_HECIBAR + 0, payload[i] & ((1 << (8 * len)) - 1));
+	write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 0x4);
 }
 
 static void
@@ -1791,7 +1801,7 @@ send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress)
 	int maxlen;
 
 	wait_heci_ready();
-	maxlen = (read32(DEFAULT_HECIBAR | 0x4) >> 24) * 4 - 4;
+	maxlen = (read32(DEFAULT_HECIBAR + 0x4) >> 24) * 4 - 4;
 
 	while (len) {
 		int cur = len;
@@ -1821,19 +1831,19 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
 	} csr;
 	int i = 0;
 
-	write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 2);
+	write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2);
 	do {
-		csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+		csr.raw = read32(DEFAULT_HECIBAR + 0xc);
 #if !REAL
 		if (i++ > 346)
 			return -1;
 #endif
 	}
 	while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);
-	*(u32 *) head = read32(DEFAULT_HECIBAR | 0x8);
+	*(u32 *) head = read32(DEFAULT_HECIBAR + 0x8);
 	if (!head->length) {
-		write32(DEFAULT_HECIBAR | 0x4,
-			read32(DEFAULT_HECIBAR | 0x4) | 2);
+		write32(DEFAULT_HECIBAR + 0x4,
+			read32(DEFAULT_HECIBAR + 0x4) | 2);
 		*packet_size = 0;
 		return 0;
 	}
@@ -1844,16 +1854,16 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
 	}
 
 	do
-		csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+		csr.raw = read32(DEFAULT_HECIBAR + 0xc);
 	while ((head->length + 3) >> 2 >
 	       csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr);
 
 	for (i = 0; i < (head->length + 3) >> 2; i++)
-		packet[i++] = read32(DEFAULT_HECIBAR | 0x8);
+		packet[i++] = read32(DEFAULT_HECIBAR + 0x8);
 	*packet_size = head->length;
 	if (!csr.csr.ready)
 		*packet_size = 0;
-	write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 4);
+	write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 4);
 	return 0;
 }
 
@@ -1941,27 +1951,27 @@ static void setup_heci_uma(struct raminfo *info)
 
 	pcie_read_config32(NORTHBRIDGE, DMIBAR);
 	if (info->memory_reserved_for_heci_mb) {
-		write32(DEFAULT_DMIBAR | 0x14,
-			read32(DEFAULT_DMIBAR | 0x14) & ~0x80);
-		write32(DEFAULT_RCBA | 0x14,
-			read32(DEFAULT_RCBA | 0x14) & ~0x80);
-		write32(DEFAULT_DMIBAR | 0x20,
-			read32(DEFAULT_DMIBAR | 0x20) & ~0x80);
-		write32(DEFAULT_RCBA | 0x20,
-			read32(DEFAULT_RCBA | 0x20) & ~0x80);
-		write32(DEFAULT_DMIBAR | 0x2c,
-			read32(DEFAULT_DMIBAR | 0x2c) & ~0x80);
-		write32(DEFAULT_RCBA | 0x30,
-			read32(DEFAULT_RCBA | 0x30) & ~0x80);
-		write32(DEFAULT_DMIBAR | 0x38,
-			read32(DEFAULT_DMIBAR | 0x38) & ~0x80);
-		write32(DEFAULT_RCBA | 0x40,
-			read32(DEFAULT_RCBA | 0x40) & ~0x80);
-
-		write32(DEFAULT_RCBA | 0x40, 0x87000080);	// OK
-		write32(DEFAULT_DMIBAR | 0x38, 0x87000080);	// OK
-		while (read16(DEFAULT_RCBA | 0x46) & 2
-		       && read16(DEFAULT_DMIBAR | 0x3e) & 2) ;
+		write32(DEFAULT_DMIBAR + 0x14,
+			read32(DEFAULT_DMIBAR + 0x14) & ~0x80);
+		write32(DEFAULT_RCBA + 0x14,
+			read32(DEFAULT_RCBA + 0x14) & ~0x80);
+		write32(DEFAULT_DMIBAR + 0x20,
+			read32(DEFAULT_DMIBAR + 0x20) & ~0x80);
+		write32(DEFAULT_RCBA + 0x20,
+			read32(DEFAULT_RCBA + 0x20) & ~0x80);
+		write32(DEFAULT_DMIBAR + 0x2c,
+			read32(DEFAULT_DMIBAR + 0x2c) & ~0x80);
+		write32(DEFAULT_RCBA + 0x30,
+			read32(DEFAULT_RCBA + 0x30) & ~0x80);
+		write32(DEFAULT_DMIBAR + 0x38,
+			read32(DEFAULT_DMIBAR + 0x38) & ~0x80);
+		write32(DEFAULT_RCBA + 0x40,
+			read32(DEFAULT_RCBA + 0x40) & ~0x80);
+
+		write32(DEFAULT_RCBA + 0x40, 0x87000080);	// OK
+		write32(DEFAULT_DMIBAR + 0x38, 0x87000080);	// OK
+		while (read16(DEFAULT_RCBA + 0x46) & 2
+		       && read16(DEFAULT_DMIBAR + 0x3e) & 2) ;
 	}
 
 	write_mchbar32(0x24, 0x10000 + info->memory_reserved_for_heci_mb);
@@ -2092,9 +2102,9 @@ static void write_testing(struct raminfo *info, int totalrank, int flip)
 	int nwrites = 0;
 	/* in 8-byte units.  */
 	u32 offset;
-	u32 base;
+	u8 *base;
 
-	base = totalrank << 28;
+	base = (u8 *)(totalrank << 28);
 	for (offset = 0; offset < 9 * 480; offset += 2) {
 		write32(base + offset * 8, get_etalon2(flip, offset));
 		write32(base + offset * 8 + 4, get_etalon2(flip, offset));
@@ -2212,8 +2222,8 @@ write_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
 {
 	int i;
 	for (i = 0; i < 2048; i++)
-		write32((totalrank << 28) | (region << 25) | (block << 16) |
-			(i << 2), get_etalon(flip, (block << 16) | (i << 2)));
+		write32p((totalrank << 28) | (region << 25) | (block << 16) |
+			 (i << 2), get_etalon(flip, (block << 16) | (i << 2)));
 }
 
 static u8
@@ -2238,7 +2248,7 @@ check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
 				    | (comp3 << 12) | (comp2 << 6) | (comp1 <<
 								      2);
 				failxor[comp1 & 1] |=
-				    read32(addr) ^ get_etalon(flip, addr);
+				    read32p(addr) ^ get_etalon(flip, addr);
 			}
 		for (i = 0; i < 8; i++)
 			if ((0xff << (8 * (i % 4))) & failxor[i / 4])
@@ -3774,13 +3784,13 @@ static void restore_274265(struct raminfo *info)
 #if REAL
 static void dmi_setup(void)
 {
-	gav(read8(DEFAULT_DMIBAR | 0x254));
-	write8(DEFAULT_DMIBAR | 0x254, 0x1);
-	write16(DEFAULT_DMIBAR | 0x1b8, 0x18f2);
+	gav(read8(DEFAULT_DMIBAR + 0x254));
+	write8(DEFAULT_DMIBAR + 0x254, 0x1);
+	write16(DEFAULT_DMIBAR + 0x1b8, 0x18f2);
 	read_mchbar16(0x48);
 	write_mchbar16(0x48, 0x2);
 
-	write32(DEFAULT_DMIBAR | 0xd68, read32(DEFAULT_DMIBAR | 0xd68) | 0x08000000);
+	write32(DEFAULT_DMIBAR + 0xd68, read32(DEFAULT_DMIBAR + 0xd68) | 0x08000000);
 
 	outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000,
 	     DEFAULT_GPIOBASE | 0x38);
@@ -3842,18 +3852,18 @@ void chipset_init(const int s3resume)
 		write_mchbar32(0x2c44, 0x1053687);
 		pcie_read_config8(GMA, 0x62);	// = 0x2
 		pcie_write_config8(GMA, 0x62, 0x2);
-		read8(DEFAULT_RCBA | 0x2318);
-		write8(DEFAULT_RCBA | 0x2318, 0x47);
-		read8(DEFAULT_RCBA | 0x2320);
-		write8(DEFAULT_RCBA | 0x2320, 0xfc);
+		read8(DEFAULT_RCBA + 0x2318);
+		write8(DEFAULT_RCBA + 0x2318, 0x47);
+		read8(DEFAULT_RCBA + 0x2320);
+		write8(DEFAULT_RCBA + 0x2320, 0xfc);
 	}
 
 	read_mchbar32(0x30);
 	write_mchbar32(0x30, 0x40);
 
 	pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc);
-	gav(read32(DEFAULT_RCBA | 0x3428));
-	write32(DEFAULT_RCBA | 0x3428, 0x1d);
+	gav(read32(DEFAULT_RCBA + 0x3428));
+	write32(DEFAULT_RCBA + 0x3428, 0x1d);
 }
 
 void raminit(const int s3resume, const u8 *spd_addrmap)
@@ -4813,17 +4823,17 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 	write_mchbar32(0xd40, IOMMU_BASE1 | 1);
 	write_mchbar32(0xdc0, IOMMU_BASE4 | 1);
 
-	write32(IOMMU_BASE1 | 0xffc, 0x80000000);
-	write32(IOMMU_BASE2 | 0xffc, 0xc0000000);
-	write32(IOMMU_BASE4 | 0xffc, 0x80000000);
+	write32p(IOMMU_BASE1 | 0xffc, 0x80000000);
+	write32p(IOMMU_BASE2 | 0xffc, 0xc0000000);
+	write32p(IOMMU_BASE4 | 0xffc, 0x80000000);
 
 #else
 	{
 		u32 eax;
-		eax = read32(0xffc + (read_mchbar32(0xd00) & ~1)) | 0x08000000;	// = 0xe911714b// OK
-		write32(0xffc + (read_mchbar32(0xd00) & ~1), eax);	// OK
-		eax = read32(0xffc + (read_mchbar32(0xdc0) & ~1)) | 0x40000000;	// = 0xe911714b// OK
-		write32(0xffc + (read_mchbar32(0xdc0) & ~1), eax);	// OK
+		eax = read32p(0xffc + (read_mchbar32(0xd00) & ~1)) | 0x08000000;	// = 0xe911714b// OK
+		write32p(0xffc + (read_mchbar32(0xd00) & ~1), eax);	// OK
+		eax = read32p(0xffc + (read_mchbar32(0xdc0) & ~1)) | 0x40000000;	// = 0xe911714b// OK
+		write32p(0xffc + (read_mchbar32(0xdc0) & ~1), eax);	// OK
 	}
 #endif
 
@@ -4870,9 +4880,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
 	}
 	u32 reg1c;
 	pcie_read_config32(NORTHBRIDGE, 0x40);	// = DEFAULT_EPBAR | 0x001 // OK
-	reg1c = read32(DEFAULT_EPBAR | 0x01c);	// = 0x8001 // OK
+	reg1c = read32p(DEFAULT_EPBAR | 0x01c);	// = 0x8001 // OK
 	pcie_read_config32(NORTHBRIDGE, 0x40);	// = DEFAULT_EPBAR | 0x001 // OK
-	write32(DEFAULT_EPBAR | 0x01c, reg1c);	// OK
+	write32p(DEFAULT_EPBAR | 0x01c, reg1c);	// OK
 	read_mchbar8(0xe08);	// = 0x0
 	pcie_read_config32(NORTHBRIDGE, 0xe4);	// = 0x316126
 	write_mchbar8(0x1210, read_mchbar8(0x1210) | 2);	// OK