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| author | Damien Zammit <damien@zamaudio.com> | 2015-05-03 21:34:38 +1000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-11-24 14:40:44 +0100 |
| commit | 62477931c88c701617445a3a23769583e7b830b5 (patch) | |
| tree | 9d988a958c75a9722675af1aec498449441c2fb4 /src/northbridge/intel/pineview/bootblock.c | |
| parent | 0cf0805e924b834c30fe290412e94e42f8f49cfb (diff) | |
| download | coreboot-62477931c88c701617445a3a23769583e7b830b5.tar.xz | |
northbridge/intel/pineview: Add minimal Pineview northbridge
Based on i945. Tested on Intel D510MO mainboard,
board boots to UART console with this code.
Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/10073
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel/pineview/bootblock.c')
| -rw-r--r-- | src/northbridge/intel/pineview/bootblock.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c new file mode 100644 index 0000000000..1c04c28b98 --- /dev/null +++ b/src/northbridge/intel/pineview/bootblock.c @@ -0,0 +1,8 @@ +#include <arch/io.h> +#define PCIEXBAR 0x60 + +static void bootblock_northbridge_init(void) +{ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, + CONFIG_MMCONF_BASE_ADDRESS | 4 | 1); +} |