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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-15 20:14:33 +0100 |
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committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-25 15:49:27 +0000 |
commit | 99e578e3c1697028957f25efc7c14d1cb4d405dc (patch) | |
tree | 44853df46744994d5caf3172a579f9d92252155b /src/northbridge/intel/pineview/bootblock.c | |
parent | c752c500fbcc055e8cdfb30a2e523e8a9349b79f (diff) | |
download | coreboot-99e578e3c1697028957f25efc7c14d1cb4d405dc.tar.xz |
nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
This adds a file i82801gx/bootblock_gcc.c since other targets that
don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled
bootblock.c.
Tested on Foxconn D41S.
Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/pineview/bootblock.c')
-rw-r--r-- | src/northbridge/intel/pineview/bootblock.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index bd76fb933c..bd510b00ee 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -12,11 +12,13 @@ */ #include <device/pci_ops.h> -#define PCIEXBAR 0x60 +#include <cpu/intel/car/bootblock.h> +#include "pineview.h" + #define MMCONF_256_BUSSES 16 #define ENABLE 1 -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); |