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author | Angel Pons <th3fanbus@gmail.com> | 2020-03-09 21:39:44 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 13:09:19 +0000 |
commit | 39ff703aa989ebdc056dd27e181fd135a551f522 (patch) | |
tree | 61c38b71557a22d5b553f17849c12ffc802cec8e /src/northbridge/intel/pineview/northbridge.c | |
parent | 099975debd89e72a1f2ea3a62dc1b9685b95533f (diff) | |
download | coreboot-39ff703aa989ebdc056dd27e181fd135a551f522.tar.xz |
nb/intel/pineview: Clean up code and comments
- Reformat some lines of code
- Put names to all MCHBAR registers in a separate file
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
- Align a bunch of things
Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected.
Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/pineview/northbridge.c')
-rw-r--r-- | src/northbridge/intel/pineview/northbridge.c | 47 |
1 files changed, 24 insertions, 23 deletions
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 0b9de19e97..cde2a2a681 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -25,7 +25,8 @@ #include <northbridge/intel/pineview/pineview.h> #include <cpu/intel/smm_reloc.h> -/* Reserve everything between A segment and 1MB: +/* + * Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) @@ -40,13 +41,14 @@ static void add_fixed_resources(struct device *dev, int index) resource = new_resource(dev, index++); resource->base = (resource_t) 0xfed00000; resource->size = (resource_t) 0x00100000; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - mmio_resource(dev, index++, legacy_hole_base_k, - (0xc0000 >> 10) - legacy_hole_base_k); - reserved_ram_resource(dev, index++, 0xc0000 >> 10, - (0x100000 - 0xc0000) >> 10); + resource->flags = IORESOURCE_MEM + | IORESOURCE_RESERVE + | IORESOURCE_FIXED + | IORESOURCE_STORED + | IORESOURCE_ASSIGNED; + + mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); + reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); } static void mch_domain_read_resources(struct device *dev) @@ -72,11 +74,10 @@ static void mch_domain_read_resources(struct device *dev) tolud <<= 16; /* Top of Memory - does not account for any UMA */ - tom = pci_read_config16(mch, TOM) & 0x1ff; + tom = pci_read_config16(mch, TOM) & 0x01ff; tom <<= 27; - printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ", - touud, tolud, tom); + printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ", touud, tolud, tom); tomk = tolud >> 10; @@ -106,15 +107,14 @@ static void mch_domain_read_resources(struct device *dev) delta_cbmem = tomk - cbmem_topk; tomk -= delta_cbmem; - printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", - delta_cbmem); + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", delta_cbmem); /* Report the memory regions */ ram_resource(dev, index++, 0, 640); ram_resource(dev, index++, 768, tomk - 768); reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek); - reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); - reserved_ram_resource(dev, index++, igd_basek, gms_sizek); + reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); + reserved_ram_resource(dev, index++, igd_basek, gms_sizek); reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem); /* @@ -125,12 +125,13 @@ static void mch_domain_read_resources(struct device *dev) if (touud > top32memk) { ram_resource(dev, index++, top32memk, touud - top32memk); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud - top32memk) >> 10); + (touud - top32memk) >> 10); } if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); + printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n", + pcie_config_base, pcie_config_size); + fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } @@ -185,12 +186,12 @@ static const char *northbridge_acpi_name(const struct device *dev) } static struct device_operations pci_domain_ops = { - .read_resources = mch_domain_read_resources, - .set_resources = mch_domain_set_resources, - .init = mch_domain_init, - .scan_bus = pci_domain_scan_bus, + .read_resources = mch_domain_read_resources, + .set_resources = mch_domain_set_resources, + .init = mch_domain_init, + .scan_bus = pci_domain_scan_bus, .acpi_fill_ssdt_generator = generate_cpu_entries, - .acpi_name = northbridge_acpi_name, + .acpi_name = northbridge_acpi_name, }; static struct device_operations cpu_bus_ops = { |