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author | Angel Pons <th3fanbus@gmail.com> | 2020-03-09 21:39:44 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 13:09:19 +0000 |
commit | 39ff703aa989ebdc056dd27e181fd135a551f522 (patch) | |
tree | 61c38b71557a22d5b553f17849c12ffc802cec8e /src/northbridge/intel/pineview/pineview.h | |
parent | 099975debd89e72a1f2ea3a62dc1b9685b95533f (diff) | |
download | coreboot-39ff703aa989ebdc056dd27e181fd135a551f522.tar.xz |
nb/intel/pineview: Clean up code and comments
- Reformat some lines of code
- Put names to all MCHBAR registers in a separate file
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
- Align a bunch of things
Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected.
Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/pineview/pineview.h')
-rw-r--r-- | src/northbridge/intel/pineview/pineview.h | 35 |
1 files changed, 25 insertions, 10 deletions
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 882f886b21..41ef5d9628 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -31,6 +31,7 @@ #define SYSINFO_DIMM_X8DDS 0x06 /* Device 0:0.0 PCI configuration space (Host Bridge) */ +#define HOST_BRIDGE PCI_DEV(0, 0, 0) #define EPBAR 0x40 #define MCHBAR 0x48 @@ -38,9 +39,9 @@ #define DMIBAR 0x68 #define PMIOBAR 0x78 -#define GGC 0x52 /* GMCH Graphics Control */ +#define GGC 0x52 /* GMCH Graphics Control */ -#define DEVEN 0x54 /* Device Enable */ +#define DEVEN 0x54 /* Device Enable */ #define DEVEN_D0F0 (1 << 0) #define DEVEN_D1F0 (1 << 1) #define DEVEN_D2F0 (1 << 3) @@ -84,9 +85,10 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ -#define PEGSTS 0x214 /* 32bit */ +#define PEGSTS 0x214 /* 32 bits */ -/* Device 0:2.0 PCI configuration space (Graphics Device) */ +/* Device 0:2.0 PCI configuration space (Integrated Graphics Device) */ +#define GMCH_IGD PCI_DEV(0, 2, 0) #define GMADR 0x18 #define GTTADR 0x1c @@ -98,15 +100,28 @@ * MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ +#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) +#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) +#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) +#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) +#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) +#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) +#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) +#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) +#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) + +/* As there are many registers, define them on a separate file */ + +#include "mchbar_regs.h" /* * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) @@ -114,7 +129,7 @@ * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) @@ -229,7 +244,7 @@ struct sysinfo { u8 mvco4x; /* 0 (8x) or 1 (4x) */ }; -void pineview_early_initialization(void); +void pineview_early_init(void); u32 decode_igd_memory_size(const u32 gms); u32 decode_igd_gtt_size(const u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len); |