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authorElyes HAOUAS <ehaouas@noos.fr>2016-08-23 21:29:48 +0200
committerMartin Roth <martinroth@google.com>2016-08-31 20:30:03 +0200
commit12df9505835393239d9e9589cff39a1d1dfddac1 (patch)
treeffc470b0ff74d818cd6f0dc5cd750fd414c8d960 /src/northbridge/intel/pineview
parent5a7e72f1aef02b326a67d883d92fe8c0aad9f3a9 (diff)
downloadcoreboot-12df9505835393239d9e9589cff39a1d1dfddac1.tar.xz
northbridge/intel: Add required space before opening parenthesis '('
Change-Id: I53208ce5db06d2c65f954e6d59222924ab87722e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16304 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/pineview')
-rw-r--r--src/northbridge/intel/pineview/raminit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index e4957d2484..e1d23a5679 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -521,7 +521,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
}
if (highcas < lowcas) {
// Timings not supported by MCH, lower the frequency
- if(freq == MEM_CLOCK_800MHz) {
+ if (freq == MEM_CLOCK_800MHz) {
freq--;
PRINTK_DEBUG("Run DDR clock speed reduced due to timings\n");
} else {