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authorArthur Heymans <arthur@aheymans.xyz>2018-06-26 21:06:13 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-08-01 12:12:50 +0000
commit15e1b39e6e4c7d7d7b0bc2bc7347a1f037ec2692 (patch)
treeb2699a19e0f928834315461138cba3b2c25c96d2 /src/northbridge/intel/pineview
parentc6e13b6690e15fe32b7c7c135bea5e8a7e6d1753 (diff)
downloadcoreboot-15e1b39e6e4c7d7d7b0bc2bc7347a1f037ec2692.tar.xz
nb/intel/pineview: Don't use PCI operations on the pci_domain device
pci ops happen to work on this struct device since the device_path is an union. This patch still keeps adding the fixed resources in the pci_domain ops since moving it to the PCI ops which could properly use the function argument for PCI operations would require all PCI IDs to be added or else breakages are to be expected. Change-Id: Iea5a09c62cca102b2c211e9256295c24cf3e9fa0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27243 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/pineview')
-rw-r--r--src/northbridge/intel/pineview/northbridge.c16
1 files changed, 9 insertions, 7 deletions
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 0bba03da29..4775b155e2 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -59,20 +59,22 @@ static void mch_domain_read_resources(struct device *dev)
u16 index;
const u32 top32memk = 4 * (GiB / KiB);
+ struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0));
+
index = 3;
pci_domain_read_resources(dev);
/* Top of Upper Usable DRAM, including remap */
- touud = pci_read_config16(dev, TOUUD);
+ touud = pci_read_config16(mch, TOUUD);
touud <<= 20;
/* Top of Lower Usable DRAM */
- tolud = pci_read_config16(dev, TOLUD) & 0xfff0;
+ tolud = pci_read_config16(mch, TOLUD) & 0xfff0;
tolud <<= 16;
/* Top of Memory - does not account for any UMA */
- tom = pci_read_config16(dev, TOM) & 0x1ff;
+ tom = pci_read_config16(mch, TOM) & 0x1ff;
tom <<= 27;
printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ",
@@ -81,7 +83,7 @@ static void mch_domain_read_resources(struct device *dev)
tomk = tolud >> 10;
/* Graphics memory */
- const u16 ggc = pci_read_config16(dev, GGC);
+ const u16 ggc = pci_read_config16(mch, GGC);
const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);
tomk -= gms_sizek;
@@ -91,9 +93,9 @@ static void mch_domain_read_resources(struct device *dev)
printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
tomk -= gsm_sizek;
- const u32 tseg_basek = pci_read_config32(dev, TSEG) >> 10;
- const u32 igd_basek = pci_read_config32(dev, GBSM) >> 10;
- const u32 gtt_basek = pci_read_config32(dev, BGSM) >> 10;
+ const u32 tseg_basek = pci_read_config32(mch, TSEG) >> 10;
+ const u32 igd_basek = pci_read_config32(mch, GBSM) >> 10;
+ const u32 gtt_basek = pci_read_config32(mch, BGSM) >> 10;
/* Subtract TSEG size */
tseg_sizek = gtt_basek - tseg_basek;