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author | Duncan Laurie <dlaurie@google.com> | 2019-04-18 16:37:50 -0700 |
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committer | Duncan Laurie <dlaurie@chromium.org> | 2019-06-07 20:51:16 +0000 |
commit | c145e54f695480ac02f752a6d01e98cb37248a07 (patch) | |
tree | c60ba05b1ee70085fc6f8c9f5278e6f5d48c3d78 /src/northbridge/intel/pineview | |
parent | c1c60601eeba69b1a897fec59e00f2dcc65f90dd (diff) | |
download | coreboot-c145e54f695480ac02f752a6d01e98cb37248a07.tar.xz |
ec/google/wilco: Add UCSI support
This change adds support for the UCSI specification in order to
provide information about the Type-C port and an interface to
perform power and data role swap.
This change is split across the DSDT and SSDT, with the shared
memory and operation region declared in the SSDT after being
allocated in CBMEM.
The OS will fill in the registers in the system memory region and
then call the _DSM method wtih a read or write argument. The DSM
method will copy the required registers to/from the system memory
and the EC and perform the write or read action.
Responses from the EC will generate a new SCI with event code 0x79
which will notify this UCSI ACPI device and the OS driver will take
action to read status from the EC.
BUG=b:131083691
Change-Id: I438a2bdfaf6720acd8354e0339dcef2844b63a4e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/northbridge/intel/pineview')
0 files changed, 0 insertions, 0 deletions