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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-03 07:30:26 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-14 14:08:57 +0000
commitde640781020b10e72dd6a5cda26cab10932e94fe (patch)
treef3e43318b33a10918c906458e6b03b2a2194d7ee /src/northbridge/intel/pineview
parent91c47c0deac054d5b949d1bf1be7c0e7cbf7d545 (diff)
downloadcoreboot-de640781020b10e72dd6a5cda26cab10932e94fe.tar.xz
bootblock: Provide some common prototypes
The split of bootblock initialisation to cpu, northbridge and southbridge is not specific to intel at all, create new header <arch/bootblock.h> as AMD will want some of these too. Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/pineview')
-rw-r--r--src/northbridge/intel/pineview/bootblock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
index bd510b00ee..98085a7406 100644
--- a/src/northbridge/intel/pineview/bootblock.c
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -11,8 +11,8 @@
* GNU General Public License for more details.
*/
+#include <arch/bootblock.h>
#include <device/pci_ops.h>
-#include <cpu/intel/car/bootblock.h>
#include "pineview.h"
#define MMCONF_256_BUSSES 16