diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-29 09:09:12 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:11:33 +0000 |
| commit | 5ac723e5a4a22bc9a08098cd59de5026b18d362d (patch) | |
| tree | 1dd12f2f9c99d90dddfb08da50d7cf46264fc716 /src/northbridge/intel/pineview | |
| parent | b30fe36734df3c48ec35438052ee8b28bf7a6a44 (diff) | |
| download | coreboot-5ac723e5a4a22bc9a08098cd59de5026b18d362d.tar.xz | |
nb/intel: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I7c7fb10308a6fcd1ead292c53ed03ddc693f6f15
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/pineview')
| -rw-r--r-- | src/northbridge/intel/pineview/northbridge.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 83bc60eece..856eab3301 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -147,12 +147,8 @@ static void mch_domain_set_resources(struct device *dev) static void mch_domain_init(struct device *dev) { - u32 reg32; - /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } static const char *northbridge_acpi_name(const struct device *dev) |