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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-17 10:56:26 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-23 15:52:09 +0000 |
| commit | a342f3937e7ce159fd170ab8cd26ba799a3bc9e4 (patch) | |
| tree | 4bd4540ba11286f465272c1fbee62dbf5f9789f8 /src/northbridge/intel/pineview | |
| parent | 9856892297ad997f586a1b4dd0a494f3764a0ce2 (diff) | |
| download | coreboot-a342f3937e7ce159fd170ab8cd26ba799a3bc9e4.tar.xz | |
src: Remove unneeded whitespace
Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/pineview')
| -rw-r--r-- | src/northbridge/intel/pineview/early_init.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/pineview/raminit.c | 14 |
2 files changed, 9 insertions, 9 deletions
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 3984fb7a07..7f90529ef2 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -181,9 +181,9 @@ static void pineview_setup_bars(void) printk(BIOS_DEBUG, "Setting up static southbridge registers..."); pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */ + pci_write_config8(LPC, 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI */ pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(LPC, 0x4c /* GC */ , 0x10); /* Enable GPIOs */ + pci_write_config8(LPC, 0x4c /* GC */, 0x10); /* Enable GPIOs */ pci_write_config32(LPC, 0x88, 0x007c0291); pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 5adf865433..778b2f7f52 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -57,13 +57,13 @@ #define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) #define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0) -#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ +#define ONLY_DIMMA_IS_POPULATED(dimms, ch) (\ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) -#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ +#define ONLY_DIMMB_IS_POPULATED(dimms, ch) (\ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) -#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ +#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) (\ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) #define FOR_EACH_DIMM(idx) \ @@ -905,11 +905,11 @@ static void sdram_p_dqs(struct pllparam *pll, u8 f, u8 clk) reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9); reg32 |= ((u32) pll->dbsel[f][clk]) << dqs; MCHBAR32(0x5b4+rank*4) = (MCHBAR32(0x5b4+rank*4) & - ~( (1 << (dqs+9))|(1 << dqs) )) | reg32; + ~((1 << (dqs+9))|(1 << dqs))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs*2) + 16); MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) & - ~( (1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)) )) | reg32; + ~((1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)))) | reg32; reg8 = pll->pi[f][clk]; MCHBAR8(0x520+j) = (MCHBAR8(0x520+j) & ~0x3f) | reg8; @@ -930,11 +930,11 @@ static void sdram_p_dq(struct pllparam *pll, u8 f, u8 clk) reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9); reg32 |= ((u32) pll->dbsel[f][clk]) << dq; MCHBAR32(0x5a4+rank*4) = (MCHBAR32(0x5a4+rank*4) & - ~( (1 << (dq+9))|(1 << dq) )) | reg32; + ~((1 << (dq+9))|(1 << dq))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) & - ~( (1 << (dq*2 + 1))|(1 << (dq*2)) )) | reg32; + ~((1 << (dq*2 + 1))|(1 << (dq*2)))) | reg32; reg8 = pll->pi[f][clk]; MCHBAR8(0x500+j) = (MCHBAR8(0x500+j) & ~0x3f) | reg8; |