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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-08-06 15:35:28 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-24 10:00:31 +0000 |
| commit | 17ad4598e9d3d302cc45c86a8e11aac62928c83c (patch) | |
| tree | c2f108634585b63c50822e5bdaa2ee57291d105e /src/northbridge/intel/pineview | |
| parent | 794f56bdf5acc5d153472bb583d51bb9fe56166f (diff) | |
| download | coreboot-17ad4598e9d3d302cc45c86a8e11aac62928c83c.tar.xz | |
nb/intel/*: Account for cbmem_top alignment
Having cbmem floating between two ram regions is a bad idea and some
payloads (e.g. tianocore) even bail out on this. To overcome this issue mark the
region between tom and cbmem as uma.
Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920952
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/pineview')
| -rw-r--r-- | src/northbridge/intel/pineview/northbridge.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 4775b155e2..2647bcc968 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <console/console.h> #include <arch/io.h> #include <stdint.h> @@ -55,7 +56,7 @@ static void mch_domain_read_resources(struct device *dev) { u64 tom, touud; u32 tomk, tolud, tseg_sizek; - u32 pcie_config_base, pcie_config_size; + u32 pcie_config_base, pcie_config_size, cbmem_topk, delta_cbmem; u16 index; const u32 top32memk = 4 * (GiB / KiB); @@ -100,6 +101,16 @@ static void mch_domain_read_resources(struct device *dev) /* Subtract TSEG size */ tseg_sizek = gtt_basek - tseg_basek; tomk -= tseg_sizek; + printk(BIOS_DEBUG, "TSEG decoded, subtracting %dM\n", tseg_sizek >> 10); + + /* cbmem_top can be shifted downwards due to alignment. + Mark the region between cbmem_top and tomk as unusable */ + cbmem_topk = (uint32_t)cbmem_top() >> 10; + delta_cbmem = tomk - cbmem_topk; + tomk -= delta_cbmem; + + printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", + delta_cbmem); /* Report the memory regions */ ram_resource(dev, index++, 0, 640); @@ -107,6 +118,7 @@ static void mch_domain_read_resources(struct device *dev) reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek); reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); reserved_ram_resource(dev, index++, igd_basek, gms_sizek); + reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem); /* * If > 4GB installed then memory from TOLUD to 4GB |