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authorElyes HAOUAS <ehaouas@noos.fr>2019-05-05 17:37:49 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-05-06 10:39:01 +0000
commit45b824d69433a630147dd690f6b5993bc2d4bb76 (patch)
treed1ceebb6eedcc9aa0818b4a1326400123b4c9042 /src/northbridge/intel/pineview
parent0a7543db2d9938fe449d800f0b2e61ffefd7b822 (diff)
downloadcoreboot-45b824d69433a630147dd690f6b5993bc2d4bb76.tar.xz
src: Remove unused include <halt.h>
Change-Id: I2f142cc80692e60eb0f81f57339a247f6ef4a524 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/pineview')
-rw-r--r--src/northbridge/intel/pineview/romstage.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index bdb685b252..a3e6c39172 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -23,7 +23,6 @@
#include <device/pci_ops.h>
#include <cbmem.h>
#include <cf9_reset.h>
-#include <halt.h>
#include <romstage_handoff.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/gpio.h>