summaryrefslogtreecommitdiff
path: root/src/northbridge/intel/pineview
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-18 15:26:48 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-03-27 08:26:16 +0000
commitf5cf60f25b8c77e0c90094e3326c5bc0e37cb383 (patch)
tree63967d01ebab0c1cdb41c58d4c52fea1d45616a4 /src/northbridge/intel/pineview
parent12724d6ad6fd6ab0ca8ea5d258c0ca7cce807441 (diff)
downloadcoreboot-f5cf60f25b8c77e0c90094e3326c5bc0e37cb383.tar.xz
Move calls to quick_ram_check() before CBMEM init
After raminit completes, do a read-modify-write test just below CBMEM top address. If test fails, die(). Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/northbridge/intel/pineview')
-rw-r--r--src/northbridge/intel/pineview/romstage.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index cf1da63f85..e6a344e738 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -18,7 +18,6 @@
*/
#include <arch/io.h>
-#include <lib.h>
#include <timestamp.h>
#include <console/console.h>
#include <device/pci_ops.h>
@@ -105,8 +104,6 @@ void mainboard_romstage_entry(unsigned long bist)
post_code(0x31);
- quick_ram_check();
-
mb_pirq_setup();
rcba_config();