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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-22 22:48:35 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-11-18 21:00:30 +0100
commitbfca67078cfddc18994fa6bbe9094a2ecca275a3 (patch)
treed251389ecf692dab90b16af9dfe643fd1b71386e /src/northbridge/intel/sandybridge/Kconfig
parentde01136484c58d13457ccf1e42fdb2310f3cbe65 (diff)
downloadcoreboot-bfca67078cfddc18994fa6bbe9094a2ecca275a3.tar.xz
intel/sandybridge post-car: Redo MTRR settings and stack selection
Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Also fixes regression of slower S3 resume path after commit 9b99152 intel/sandybridge: Use common ACPI S3 recovery Skipping low memory backup and using stage cache for ramstage decreases time spent on S3 resume path by 50 ms on samsung/lumpy. Change-Id: I2afee3662e73e8e629188258b2f4119e02d60305 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15790 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/sandybridge/Kconfig')
-rw-r--r--src/northbridge/intel/sandybridge/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 2fb455159e..d7af9f2329 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE
select CPU_INTEL_MODEL_206AX
select HAVE_DEBUG_RAM_SETUP
select INTEL_GMA_ACPI
+ select RELOCATABLE_RAMSTAGE
config NORTHBRIDGE_INTEL_IVYBRIDGE
bool
@@ -31,6 +32,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
select CPU_INTEL_MODEL_306AX
select HAVE_DEBUG_RAM_SETUP
select INTEL_GMA_ACPI
+ select RELOCATABLE_RAMSTAGE
if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE