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author | Nico Huber <nico.huber@secunet.com> | 2015-10-26 12:59:49 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-11-04 18:17:25 +0100 |
commit | 9d9ce0d6d2ed3e5a2a81407a835a7e8d6490fe1f (patch) | |
tree | 08a3f59684018da39e1fbd43cecec24cde5b5315 /src/northbridge/intel/sandybridge/acpi.c | |
parent | bb9469c450a12b876fca3a8c5e02af97c0ef36a1 (diff) | |
download | coreboot-9d9ce0d6d2ed3e5a2a81407a835a7e8d6490fe1f.tar.xz |
nb/intel/sandybridge: Add ACPI DMAR table
Add a DMAR table to advertise IOMMU and IRQ remapping capabilities to
the OS.
Tested with kontron/ktqm77. Under Linux, the table is detected and
interrupt remapping is enabled automatically.
Change-Id: Id6ee601a0a8543ed09c6bb8d308a3a3549fc34e5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12195
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/acpi.c')
-rw-r--r-- | src/northbridge/intel/sandybridge/acpi.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index dc1d668dc2..eebf99c052 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -28,6 +28,7 @@ #include "sandybridge.h" #include <cbmem.h> #include <drivers/intel/gma/intel_bios.h> +#include <southbridge/intel/bd82x6x/pch.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -207,3 +208,52 @@ void *igd_make_opregion(void) init_igd_opregion(opregion); return opregion; } + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + const struct device *const igfx = dev_find_slot(0, PCI_DEVFN(2, 0)); + + if (igfx && igfx->enabled) { + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); + current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0); + current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 1); + acpi_dmar_drhd_fixup(tmp, current); + } + + const unsigned long tmp = current; + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE2); + current += acpi_create_dmar_drhd_ds_ioapic(current, + 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + size_t i; + for (i = 0; i < 8; ++i) + current += acpi_create_dmar_drhd_ds_msi_hpet(current, + 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, i); + acpi_dmar_drhd_fixup(tmp, current); + + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long northbridge_write_acpi_tables(struct device *const dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + const u32 capid0_a = pci_read_config32(dev, 0xe4); + if (capid0_a & (1 << 23)) + return current; + + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, dmar); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + + return current; +} |