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| author | Felix Held <felix-coreboot@felixheld.de> | 2019-12-28 18:09:47 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-12-29 12:19:14 +0000 |
| commit | 4902fee4412eb15bee5f5e164302730de0ce195e (patch) | |
| tree | 505f51579902c768bdef21d22559e0cc79c5e809 /src/northbridge/intel/sandybridge/finalize.c | |
| parent | cf425783c8896173a74103bd4936d0c205954f83 (diff) | |
| download | coreboot-4902fee4412eb15bee5f5e164302730de0ce195e.tar.xz | |
nb/intel/sandybridge: add and use defines for PCI_DEV(0,0,0) registers
This patch didn't change the resulting binary for an X230 when using
TIMELESS_BUILD=1
Change-Id: Ibeb10c3e0c04dec76892a86fa39e60543b2ee2f5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge/intel/sandybridge/finalize.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/finalize.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index a8f8603f02..50fc7555f6 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -21,18 +21,18 @@ void intel_sandybridge_finalize_smm(void) { - pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pci_or_config16(PCI_DEV_SNB, 0x58, 1 << 2); /* PAVP Lock */ - pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0); + pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2); + pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0); pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0); + pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0); + pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0); + pci_or_config32(PCI_DEV_SNB, TOUUD, 1 << 0); + pci_or_config32(PCI_DEV_SNB, BDSM, 1 << 0); + pci_or_config32(PCI_DEV_SNB, BGSM, 1 << 0); + pci_or_config32(PCI_DEV_SNB, TSEGMB, 1 << 0); + pci_or_config32(PCI_DEV_SNB, TOLUD, 1 << 0); MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ |