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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-02-27 23:45:20 +0100 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-02-28 00:00:30 +0100 |
| commit | fd611f9c2c8c751069c6cd1634a3e3e523ff098b (patch) | |
| tree | 3e1d3d844987a6f02d406e13f68aa37e3f55ec7e /src/northbridge/intel/sandybridge/northbridge.c | |
| parent | 9c29cfae8cc6214478a0a555e6901779eb19ef54 (diff) | |
| download | coreboot-fd611f9c2c8c751069c6cd1634a3e3e523ff098b.tar.xz | |
Drop CONFIG_WRITE_HIGH_TABLES
It's been on for all boards per default since several years now
and the old code path probably doesn't even work anymore. Let's
just have one consistent way of doing things.
Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4b6808a0fb..bc63d1adae 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -259,11 +259,9 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } /* TODO We could determine how many PCIe busses we need in |