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| author | Patrick Rudolph <siro@das-labor.org> | 2015-07-28 08:01:02 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2015-10-09 08:40:19 +0000 |
| commit | 3660c0fc658e4e20ef079f762dfc7ad05c83544c (patch) | |
| tree | 1953b7a041717aa3518a06bbdd5152753bc668b1 /src/northbridge/intel/sandybridge/northbridge.c | |
| parent | a2bed346a1a45c822bc255e90a0bf6a6ae1d1d50 (diff) | |
| download | coreboot-3660c0fc658e4e20ef079f762dfc7ad05c83544c.tar.xz | |
northbridge/intel/sandybridge: Enable PEG clock-gating on demand
Activate PEG clock-gating only if all PEG devices are disabled.
Fixes system hang when trying to access PEG registers.
Test system:
* Intel Pentium CPU G2130
* Gigabyte GA-B75M-D3H
Change-Id: I7d62fbb83c16741965639cea1a0e4978d4e3d6da
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11059
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/sandybridge/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 0e0ba00cf1..76f03f3ba9 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -361,6 +361,51 @@ static void northbridge_dmi_init(struct device *dev) DMIBAR32(0x88) = reg32; } +/* Disable unused PEG devices based on devicetree */ +static void disable_peg(void) +{ + struct device *dev; + u32 reg; + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + reg = pci_read_config32(dev, DEVEN); + + dev = dev_find_slot(0, PCI_DEVFN(1, 2)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG12.\n"); + reg &= ~DEVEN_PEG12; + } + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG11.\n"); + reg &= ~DEVEN_PEG11; + } + dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG10.\n"); + reg &= ~DEVEN_PEG10; + } + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling IGD.\n"); + reg &= ~DEVEN_IGD; + } + dev = dev_find_slot(0, PCI_DEVFN(6, 0)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling PEG60.\n"); + reg &= ~DEVEN_PEG60; + } + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + pci_write_config32(dev, DEVEN, reg); + if (!(reg & (DEVEN_PEG60 | DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG12))) { + /* Set the PEG clock gating bit. + * Disables the IO clock on all PEG devices. */ + MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01; + printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); + } +} + static void northbridge_init(struct device *dev) { u8 bios_reset_cpl; @@ -411,6 +456,9 @@ static void northbridge_init(struct device *dev) /* Set here before graphics PM init */ MCHBAR32(0x5500) = 0x00100001; + + /* Turn off unused devices */ + disable_peg(); } static void northbridge_enable(device_t dev) |