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| author | Patrick Rudolph <siro@das-labor.org> | 2017-06-07 09:44:07 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-27 16:09:18 +0000 |
| commit | 3e47fc9e94089476fcef4fcafa8547cbb693316b (patch) | |
| tree | 9b5016ac85e7ac31579460173718762e974f5ec1 /src/northbridge/intel/sandybridge/northbridge.c | |
| parent | 33906d2347e6cd32a7dd4cda1f7bd27b2d660241 (diff) | |
| download | coreboot-3e47fc9e94089476fcef4fcafa8547cbb693316b.tar.xz | |
nb/intel/sandybridge: Fill in acpi_name
Fill in acpi_name to return proper ACPI names. To be used with
SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
GFX0 is used in drivers/intel/gma/acpi/pch.asl.
MCHC is used in nb/intel/sandybridge/acpi/hostbridge.asl.
Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5c5f41ad4a..635e321c77 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -242,6 +242,22 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } +static const char *northbridge_acpi_name(struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): + return "MCHC"; + } + + return NULL; +} + /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. @@ -252,8 +268,9 @@ static struct device_operations pci_domain_ops = { .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .ops_pci_bus = pci_bus_default_ops, .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_name = northbridge_acpi_name, }; static void mc_read_resources(device_t dev) |