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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-06-27 08:20:09 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-09-11 07:09:47 +0200 |
| commit | 42f4651434877085f2a44939375bffeeecdb2c37 (patch) | |
| tree | 2a2dcf63118fd7dc61dd5d092ef0d55c081cb71b /src/northbridge/intel/sandybridge/northbridge.c | |
| parent | 2b790f651230589fd66e8121745986b8a939b13b (diff) | |
| download | coreboot-42f4651434877085f2a44939375bffeeecdb2c37.tar.xz | |
CBMEM northbridges: Remove references to global high_tables_base
Use the new helper function set_top_of_ram() to remove remaining
uses of high_tables_base and _size under northbridge/.
Change-Id: I6b0d9615002ed2aff578c5811d7bd43dd2594453
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3561
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index e3290d8985..4cd86cd9df 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -274,9 +274,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; - high_tables_size = HIGH_MEMORY_SIZE; + set_top_of_ram(tomk * 1024); } /* TODO We could determine how many PCIe busses we need in |