intel/nehalem,sandybridge: Move stage_cache support function

Let garbage-collection take care of stage_cache_external_region()
if it is no needed and move implementation to a suitable file already
building for needed stages.

Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE and
(unused) aliasing of CONFIG_IED_REGION_SIZE as IED_SIZE.

Change-Id: Idf00ba3180d8c3bc974dd3c5ca5f98a6c08bf34d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34672
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 22 deletions

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 5aa06c8e4f..233384cd15 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -444,28 +444,6 @@ static void northbridge_init(struct device *dev)
 	MCHBAR32(0x5500) = 0x00100001;
 }
 
-static u32 northbridge_get_base_reg(struct device *dev, int reg)
-{
-	u32 value;
-
-	value = pci_read_config32(dev, reg);
-	/* Base registers are at 1MiB granularity. */
-	value &= ~((1 << 20) - 1);
-	return value;
-}
-
-u32 northbridge_get_tseg_base(void)
-{
-	struct device *dev = pcidev_on_root(0, 0);
-
-	return northbridge_get_base_reg(dev, TSEG);
-}
-
-u32 northbridge_get_tseg_size(void)
-{
-	return CONFIG_SMM_TSEG_SIZE;
-}
-
 void northbridge_write_smram(u8 smram)
 {
 	pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram);