diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-06-23 20:14:07 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-24 23:50:59 +0200 |
| commit | fe7b5d2fa6705a2b553244dda0452ca55c5730a2 (patch) | |
| tree | 51a6edff273d0f348dbf8db8c48731550da0e726 /src/northbridge/intel/sandybridge/northbridge.c | |
| parent | 22935e1f43c2b0873dfa9b5f176df5616ce7a041 (diff) | |
| download | coreboot-fe7b5d2fa6705a2b553244dda0452ca55c5730a2.tar.xz | |
Ivybridge: fix workaround and enable PAIR
MCHBAR 0x5f10[7:0] should be set to 0x30 for ivybridge
and 0x20 for sandybridge. Move this code to ramstage
and set it per-chipset.
Power Aware Interrupt Routing is supported in ivybridge,
enable it and set fixed priority.
Boot on ivybridge device and read MCHBAR 0x5f10:
mmio_read8 0xfed15f10
0x30
And verify PAIR is enabled (bit4=1):
mmio_read8 0xfed15418
0x24
Change-Id: If017d5ce2bd5ab5092c86f657434f2b645ee6613
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1303
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index baf4348f96..bfb2166a11 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -388,9 +388,28 @@ static void northbridge_dmi_init(struct device *dev) static void northbridge_init(struct device *dev) { u8 bios_reset_cpl; + u32 bridge_type; northbridge_dmi_init(dev); + bridge_type = MCHBAR32(0x5f10); + bridge_type &= ~0xff; + + if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { + /* Enable Power Aware Interrupt Routing */ + u8 pair = MCHBAR8(0x5418); + pair &= ~0xf; /* Clear 3:0 */ + pair |= 0x4; /* Fixed Priority */ + MCHBAR8(0x5418) = pair; + + /* 30h for IvyBridge */ + bridge_type |= 0x30; + } else { + /* 20h for Sandybridge */ + bridge_type |= 0x20; + } + MCHBAR32(0x5f10) = bridge_type; + /* * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU * that BIOS has initialized memory and power management |