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author | Nico Huber <nico.huber@secunet.com> | 2015-10-21 11:49:23 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-11-04 18:17:19 +0100 |
commit | bb9469c450a12b876fca3a8c5e02af97c0ef36a1 (patch) | |
tree | 27fc7a5c188df69a87584e9fbcf119a56f51d8f1 /src/northbridge/intel/sandybridge/northbridge.c | |
parent | b2dae79301d2bb19e17a4c8960b11a16800574f8 (diff) | |
download | coreboot-bb9469c450a12b876fca3a8c5e02af97c0ef36a1.tar.xz |
nb/intel/sandybridge: Enable basic IOMMU support
Sandy Bridge and Ivy Bridge processors have two IOMMU units. One for the
integrated graphics controller and one for all other PCI devices. Assign
resources for both IOMMUs and apply some quirks.
Tested with kontron/ktqm77 and a Muen based system that makes use of the
IOMMUs. Not tested on Sandy Bridge, but register dumps show the same
settings that are applied here.
Change-Id: I43b5e20b750e7529f448acac35de173185678fd9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12194
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/northbridge.c')
-rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 09830de102..c718353b8d 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -127,6 +127,13 @@ static void add_fixed_resources(struct device *dev, int index) /* Required for SandyBridge sighting 3715511 */ bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); + + /* Reserve IOMMU BARs */ + const u32 capid0_a = pci_read_config32(dev, 0xe4); + if (!(capid0_a & (1 << 23))) { + mmio_resource(dev, index++, IOMMU_BASE1 >> 10, 4); + mmio_resource(dev, index++, IOMMU_BASE2 >> 10, 4); + } } static void pci_domain_set_resources(device_t dev) |