diff options
author | Vladimir Serbinenko <phcoder@gmail.com> | 2016-02-10 01:36:25 +0100 |
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committer | Martin Roth <martinroth@google.com> | 2016-02-12 04:20:57 +0100 |
commit | ffbb3c0b8abea621eb7a1583d630cf06c8cbfbbc (patch) | |
tree | 9a45adcee57358dd8ebafc4201db2cbd0beef679 /src/northbridge/intel/sandybridge/raminit.c | |
parent | 622eea7e815af39dbee290eddc487baab5e8a5f5 (diff) | |
download | coreboot-ffbb3c0b8abea621eb7a1583d630cf06c8cbfbbc.tar.xz |
Merge sandy/ivybridge romstage flow for MRC and non-MRC.
Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13656
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit.c')
-rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index aae963e239..7490ff7f29 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -24,12 +24,14 @@ #include <cbfs.h> #include <halt.h> #include <ip_checksum.h> +#include <timestamp.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> #include "raminit_native.h" #include "sandybridge.h" #include <delay.h> #include <lib.h> +#include <device/device.h> /* Management Engine is in the southbridge */ #include "southbridge/intel/bd82x6x/me.h" @@ -37,6 +39,7 @@ #include "southbridge/intel/bd82x6x/smbus.h" #include "arch/cpu.h" #include "cpu/x86/msr.h" +#include <northbridge/intel/sandybridge/chip.h> /* FIXME: no ECC support. */ /* FIXME: no support for 3-channel chipsets. */ @@ -4034,3 +4037,44 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, halt(); } } + +#define HOST_BRIDGE PCI_DEVFN(0, 0) +#define DEFAULT_TCK TCK_800MHZ + +static unsigned int get_mem_min_tck(void) +{ + const struct device *dev; + const struct northbridge_intel_sandybridge_config *cfg; + + dev = dev_find_slot(0, HOST_BRIDGE); + if (!(dev && dev->chip_info)) + return DEFAULT_TCK; + + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (cfg->max_mem_clock_mhz == 0) + return DEFAULT_TCK; + + if (cfg->max_mem_clock_mhz >= 800) + return TCK_800MHZ; + else if (cfg->max_mem_clock_mhz >= 666) + return TCK_666MHZ; + else if (cfg->max_mem_clock_mhz >= 533) + return TCK_533MHZ; + return TCK_400MHZ; +} + +void perform_raminit(int s3resume) +{ + spd_raw_data spd[4]; + + post_code(0x3a); + + memset (spd, 0, sizeof (spd)); + mainboard_get_spd(spd); + + timestamp_add_now(TS_BEFORE_INITRAM); + + init_dram_ddr3(spd, 1, get_mem_min_tck(), s3resume); +} |