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author | Patrick Rudolph <siro@das-labor.org> | 2017-10-28 16:36:09 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-14 10:02:07 +0000 |
commit | 05d4bf7ea76114dcbd21f8302e7152f40d806f18 (patch) | |
tree | 77e6fa56dd6150a4010aa7f59f2de2183dc6c04e /src/northbridge/intel/sandybridge/raminit_common.c | |
parent | 48d5b8d463ceccf5bf38f0d45490cb9d6185979e (diff) | |
download | coreboot-05d4bf7ea76114dcbd21f8302e7152f40d806f18.tar.xz |
nb/intel/sandybridge/raminit: Add ECC detection support
Add support for detection ECC capability and forced ECC mode.
Print the ECC mode in verbose debugging mode.
Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/22214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.c')
-rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4ba5b5900f..9642a55b31 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -437,6 +437,32 @@ static unsigned int get_mmio_size(void) return cfg->pci_mmio_size; } +/* + * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. + * The ME/PCU/.. has the ability to change this. + * Return 0: ECC is optional + * Return 1: ECC is forced + */ +bool get_host_ecc_forced(void) +{ + /* read Capabilities A Register */ + const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); + return !!(reg32 & (1 << 24)); +} + +/* + * Returns the ECC capability. + * The ME/PCU/.. has the ability to change this. + * Return 0: ECC is disabled + * Return 1: ECC is possible + */ +bool get_host_ecc_cap(void) +{ + /* read Capabilities A Register */ + const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); + return !(reg32 & (1 << 25)); +} + void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) { u32 reg, val, reclaim, tom, gfxstolen, gttsize; |