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author | Kane Chen <kane.chen@intel.com> | 2017-10-05 10:17:07 +0800 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-12 02:45:41 +0000 |
commit | f73bc0b2d103705a557142461d19496b59adda81 (patch) | |
tree | 55c5e9a92db40996ffe1f0305e46a538f4d12d8a /src/northbridge/intel/sandybridge/raminit_common.c | |
parent | 6754e4ea2008f67c0630fdac976456649a5ac95a (diff) | |
download | coreboot-f73bc0b2d103705a557142461d19496b59adda81.tar.xz |
soc/intel/skylake: Enable bus master for sata
The bus master needs to be enabled so that
the busy bit in AHCI PORT_TFDATA will be cleared
by controller when depthcharge tries to wait
for sata to complete spin-up during AHCI init.
Otherwise, the timeout will happen and cause
5 seconds delay in depthcharge.
BUG=b:37639063
BRANCH=none
TEST=verify that the sata timeout is gone in
depthcharge
Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.c')
0 files changed, 0 insertions, 0 deletions