diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-03-24 11:12:09 +0100 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-04-19 09:46:42 +0000 |
commit | fc9302465ba1e78f9a99440e1898b3714861290d (patch) | |
tree | f7d827b75cccc6eeee34ead5c0ac2e874dfac541 /src/northbridge/intel/sandybridge/raminit_common.c | |
parent | 64ba44f7fb7a64c5cc1e9155758b57589320b1a5 (diff) | |
download | coreboot-fc9302465ba1e78f9a99440e1898b3714861290d.tar.xz |
nb/intel/sandybridge: Refactor get_mem_min_tck
It is not necessary to pass its value around various function calls.
Move it closer to where it is actually used, so as to make it static.
Also, use config_of_soc and flip the branches of the first conditional.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I5c49c943c87218d4d40d3168bd8b7b900b0ec2e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39851
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.c')
-rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 69 |
1 files changed, 0 insertions, 69 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 51f33629f1..087ba2b550 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -358,75 +358,6 @@ void dram_zones(ramctr_timing *ctrl, int training) } } -#define DEFAULT_TCK TCK_800MHZ - -unsigned int get_mem_min_tck(void) -{ - u32 reg32; - u8 rev; - const struct device *dev; - const struct northbridge_intel_sandybridge_config *cfg = NULL; - - dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->max_mem_clock_mhz == 0) { - - if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) - return TCK_1333MHZ; - - rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); - - if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { - /* Read Capabilities A Register DMFC bits */ - reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); - reg32 &= 0x7; - - switch (reg32) { - case 7: return TCK_533MHZ; - case 6: return TCK_666MHZ; - case 5: return TCK_800MHZ; - /* Reserved */ - default: - break; - } - } else { - /* Read Capabilities B Register DMFC bits */ - reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); - reg32 = (reg32 >> 4) & 0x7; - - switch (reg32) { - case 7: return TCK_533MHZ; - case 6: return TCK_666MHZ; - case 5: return TCK_800MHZ; - case 4: return TCK_933MHZ; - case 3: return TCK_1066MHZ; - case 2: return TCK_1200MHZ; - case 1: return TCK_1333MHZ; - /* Reserved */ - default: - break; - } - } - return DEFAULT_TCK; - } else { - if (cfg->max_mem_clock_mhz >= 1066) - return TCK_1066MHZ; - else if (cfg->max_mem_clock_mhz >= 933) - return TCK_933MHZ; - else if (cfg->max_mem_clock_mhz >= 800) - return TCK_800MHZ; - else if (cfg->max_mem_clock_mhz >= 666) - return TCK_666MHZ; - else if (cfg->max_mem_clock_mhz >= 533) - return TCK_533MHZ; - else - return TCK_400MHZ; - } -} - #define DEFAULT_PCI_MMIO_SIZE 2048 static unsigned int get_mmio_size(void) |