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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-12-24 10:42:57 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-26 21:35:24 +0000 |
| commit | 7539b8c3914ca949b2cb1172f3c9c539cee48d4b (patch) | |
| tree | 5cf3ac38317c26a917b5adcf56bb9508ac7205cb /src/northbridge/intel/sandybridge/raminit_mrc.c | |
| parent | a20e0b288b50107141fdfa10346900c1cf7ed748 (diff) | |
| download | coreboot-7539b8c3914ca949b2cb1172f3c9c539cee48d4b.tar.xz | |
nb/intel/sandybridge: Use common mrc cache functions
This uses the functions in include/mrc_cache.h instead of
northbidge/intel/common/mrc_cache.h
Tested working on Lenovo Thinkpad x220, mrc_cache region gets written
and S3 resume still works fine.
Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_mrc.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 901a083c2b..61f761e117 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -25,7 +25,7 @@ #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> -#include <northbridge/intel/common/mrc_cache.h> +#include <mrc_cache.h> #include <halt.h> #include <timestamp.h> #include "raminit.h" @@ -51,12 +51,16 @@ #define CMOS_OFFSET_MRC_SEED_CHK 160 #endif +#define MRC_CACHE_VERSION 0 + void save_mrc_data(struct pei_data *pei_data) { u16 c1, c2, checksum; /* Save the MRC S3 restore data to cbmem */ - store_current_mrc_cache(pei_data->mrc_output, pei_data->mrc_output_len); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, + pei_data->mrc_output, + pei_data->mrc_output_len); /* Save the MRC seed values to CMOS */ cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed); @@ -80,7 +84,7 @@ void save_mrc_data(struct pei_data *pei_data) static void prepare_mrc_cache(struct pei_data *pei_data) { - struct mrc_data_container *mrc_cache; + struct region_device rdev; u16 c1, c2, checksum, seed_checksum; // preset just in case there is an error @@ -113,17 +117,17 @@ static void prepare_mrc_cache(struct pei_data *pei_data) return; } - if ((mrc_cache = find_current_mrc_cache()) == NULL) { + if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, + &rdev)) { /* error message printed in find_current_mrc_cache */ return; } - pei_data->mrc_input = mrc_cache->mrc_data; - pei_data->mrc_input_len = mrc_cache->mrc_data_size; + pei_data->mrc_input = rdev_mmap_full(&rdev); + pei_data->mrc_input_len = region_device_sz(&rdev); - printk(BIOS_DEBUG, "%s: at %p, size %x checksum %04x\n", - __func__, pei_data->mrc_input, - pei_data->mrc_input_len, mrc_cache->mrc_checksum); + printk(BIOS_DEBUG, "%s: at %p, size %x\n", + __func__, pei_data->mrc_input, pei_data->mrc_input_len); } static const char* ecc_decoder[] = { |