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| author | Felix Held <felix-coreboot@felixheld.de> | 2019-12-30 17:30:16 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-01 16:09:00 +0000 |
| commit | dee167ee392be3350996507c22d74e5aef08248a (patch) | |
| tree | 78d72af58484805274dc923767772dd844bf95ce /src/northbridge/intel/sandybridge/raminit_mrc.c | |
| parent | 85e1491eba241adcebe9c0a65dd5d5b85c0a6928 (diff) | |
| download | coreboot-dee167ee392be3350996507c22d74e5aef08248a.tar.xz | |
nb/intel/sandybridge: add and use more MCHBAR register defines
Change-Id: Ie0a9be0899830a2bf9a994d10c417b0968d1cd47
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_mrc.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 84100e7ef6..cab5588ced 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -149,9 +149,9 @@ static void report_memory_config(void) u32 addr_decoder_common, addr_decode_ch[2]; int i; - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); |