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author | Stefan Reinauer <reinauer@chromium.org> | 2012-05-10 11:31:40 -0700 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-11 00:29:44 +0200 |
commit | 1244f4b52fe423eeac2621672aa1786232f2ca0b (patch) | |
tree | f5ed1bae7f1dc02c261a5c92258557440c43c6e9 /src/northbridge/intel/sandybridge/sandybridge.h | |
parent | 1c56d9b1029b344b92bc1cd1acb2fe52ce0c0e2d (diff) | |
download | coreboot-1244f4b52fe423eeac2621672aa1786232f2ca0b.tar.xz |
Rework Sandybridge MRC cache handling
- Separate Sandybridge from ChromeOS a bit
The Sandybridge code depends on chromeos features a whole lot.
As a first step, provide a code path to look up the MRC cache
without depending on u-boot.
- Move mrc cache handling to separate file
This enables us to handle the MRC cache from ramstage,
where we can write the flash safely (eg. to update the
cache).
Also teach it to lookup the current MRC cache from CBMEM,
as the original data block isn't available anymore.
After all the preparations, finally write to the SPI
as necessary. It's a simple round robin wear levelling
that erases the entire MRC cache region when it's full
and starts from the beginning.
Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1001
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/sandybridge.h')
-rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index aa62021743..7e12416f46 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -221,6 +221,28 @@ void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); void report_platform_info(void); #endif /* !__SMM__ */ + + +#define MRC_DATA_ALIGN 0x1000 +#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24)) + +struct mrc_data_container { + u32 mrc_signature; // "MRCD" + u32 mrc_data_size; // Actual total size of this structure + u32 mrc_checksum; // IP style checksum + u32 reserved; // For header alignment + u8 mrc_data[0]; // Variable size, platform/run time dependent. +} __attribute__ ((packed)); + +struct mrc_data_container *next_mrc_block(struct mrc_data_container *mrc_cache); +int is_mrc_cache(struct mrc_data_container *mrc_cache); +u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr); +struct mrc_data_container *find_next_mrc_cache(void); +struct mrc_data_container *find_current_mrc_cache(void); +#if !defined(__PRE_RAM__) +void update_mrc_cache(void); +#endif + #endif #endif #endif |