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| author | Subrata Banik <subrata.banik@intel.com> | 2018-12-10 14:11:35 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-13 04:32:57 +0000 |
| commit | 53b08c347f54970cf5f6ce35b8e1a1fe5f8a11f9 (patch) | |
| tree | b4eed19fbf1b9f35dfbdddcc43fc84469176ec59 /src/northbridge/intel/sandybridge | |
| parent | e3110b862071ae0797afb0688495315a7dd47739 (diff) | |
| download | coreboot-53b08c347f54970cf5f6ce35b8e1a1fe5f8a11f9.tar.xz | |
cpuid: Add helper function for cpuid(1) functions
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 9 |
2 files changed, 6 insertions, 11 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 46d5de8c4b..5f7fd0a8ca 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -19,6 +19,7 @@ #include <commonlib/region.h> #include <bootmode.h> #include <string.h> +#include <arch/cpu.h> #include <arch/io.h> #include <cbmem.h> #include <halt.h> @@ -287,7 +288,6 @@ static void init_dram_ddr3(int min_tck, int s3resume) spd_raw_data spds[4]; struct region_device rdev; ramctr_timing *ctrl_cached; - struct cpuid_result cpures; int err; u32 cpu; @@ -369,8 +369,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) ctrl.tCK = min_tck; /* Get architecture */ - cpures = cpuid(1); - cpu = cpures.eax; + cpu = cpu_get_cpuid(); ctrl.sandybridge = IS_SANDY_CPU(cpu); /* Get DDR3 SPD data */ @@ -391,8 +390,7 @@ static void init_dram_ddr3(int min_tck, int s3resume) ctrl.tCK = min_tck; /* Get architecture */ - cpures = cpuid(1); - cpu = cpures.eax; + cpu = cpu_get_cpuid(); ctrl.sandybridge = IS_SANDY_CPU(cpu); /* Reset DDR3 frequency */ diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 071f360327..4ce059a322 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <string.h> +#include <arch/cpu.h> #include <arch/io.h> #include <northbridge/intel/sandybridge/chip.h> #include <device/pci_def.h> @@ -190,14 +191,12 @@ void dram_xover(ramctr_timing * ctrl) static void dram_odt_stretch(ramctr_timing *ctrl, int channel) { - struct cpuid_result cpures; u32 addr, cpu, stretch; stretch = ctrl->ref_card_offset[channel]; /* ODT stretch: Delay ODT signal by stretch value. * Useful for multi DIMM setups on the same channel. */ - cpures = cpuid(1); - cpu = cpures.eax; + cpu = cpu_get_cpuid(); if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) { if (stretch == 2) stretch = 3; @@ -3020,11 +3019,9 @@ void set_scrambling_seed(ramctr_timing * ctrl) void set_4f8c(void) { - struct cpuid_result cpures; u32 cpu; - cpures = cpuid(1); - cpu = (cpures.eax); + cpu = cpu_get_cpuid(); if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { MCHBAR32(0x4f8c) = 0x141D1519; } else { |