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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2015-05-29 16:18:01 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2015-06-09 19:52:27 +0200 |
| commit | c16e9dfa18cb37b40ef7eef87f22385215b04ec2 (patch) | |
| tree | 9d9445c8bf36bb359b6fdc6f84bb3e0095962b23 /src/northbridge/intel/sandybridge | |
| parent | 4fbac465246d3cdfc91d4331be5a567f8783cc6f (diff) | |
| download | coreboot-c16e9dfa18cb37b40ef7eef87f22385215b04ec2.tar.xz | |
Create i945-ivy smm tseg init based on ivy code.
CPU-side logic is unchanged for this range of CPUs as long as all of them
use TSEG (or ASEG, just needs to be consistent). So uplift 206ax code while
extracting southbridge and APIC code into separate functions.
Change-Id: Ib365681d1da8115922c557fddcc59afc156826da
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10465
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 28 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 11 |
2 files changed, 28 insertions, 11 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7d257f6fe3..0e0ba00cf1 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -36,6 +36,7 @@ #include <cbmem.h> #include "chip.h" #include "sandybridge.h" +#include <cpu/intel/smm/gen1/smi.h> static int bridge_revision_id = -1; @@ -432,6 +433,33 @@ static void northbridge_enable(device_t dev) #endif } +static u32 northbridge_get_base_reg(device_t dev, int reg) +{ + u32 value; + + value = pci_read_config32(dev, reg); + /* Base registers are at 1MiB granularity. */ + value &= ~((1 << 20) - 1); + return value; +} + +void +northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size) +{ + device_t dev; + u32 bgsm; + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + *tsegmb = northbridge_get_base_reg(dev, TSEG); + bgsm = northbridge_get_base_reg(dev, BGSM); + *tseg_size = bgsm - *tsegmb; +} + +void northbridge_write_smram(u8 smram) +{ + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram); +} + static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 09894f71e4..6f8fcfc6bb 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -91,11 +91,6 @@ #define LAC 0x87 /* Legacy Access Control */ #define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define TOM 0xa0 #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ @@ -200,12 +195,6 @@ #ifndef __ASSEMBLER__ static inline void barrier(void) { asm("" ::: "memory"); } -struct ied_header { - char signature[10]; - u32 size; - u8 reserved[34]; -} __attribute__ ((packed)); - #define PCI_DEVICE_ID_SB 0x0104 #define PCI_DEVICE_ID_IB 0x0154 |