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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-10-15 17:19:41 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-01-15 15:29:52 +0100 |
commit | cb08e169cf959333206ef69d8aa82808ef797eb7 (patch) | |
tree | f025f6d243e815821ae70d8febbdb415025d7dfa /src/northbridge/intel/sandybridge | |
parent | bbf013c38fe76cf9cc107c41c17e4ac432847d28 (diff) | |
download | coreboot-cb08e169cf959333206ef69d8aa82808ef797eb7.tar.xz |
CBMEM intel: Define get_top_of_ram() once per chipset
Only have one definition of get_top_of_ram() function and compile
it using __SIMPLE_DEVICE__ for both romstage and ramstage.
Implemented like this on intel/northbridge/gm45 already.
This also adds get_top_of_ram() to i945 ramstage.
Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
-rw-r--r-- | src/northbridge/intel/sandybridge/Makefile.inc | 2 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 7 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/ram_calc.c | 31 | ||||
-rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 7 |
4 files changed, 33 insertions, 14 deletions
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index aa1739a974..37d392f32d 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -17,12 +17,14 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c +romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += mrccache.c romstage-y += early_init.c diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index a03b8a6492..7db9301c30 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -51,13 +51,6 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -unsigned long get_top_of_ram(void) -{ - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG); - return (unsigned long) tom; -} - /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c new file mode 100644 index 0000000000..3693a07355 --- /dev/null +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include "sandybridge.h" + +unsigned long get_top_of_ram(void) +{ + /* Base of TSEG is top of usable DRAM */ + u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return (unsigned long) tom; +} diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 07172fc768..3b6557199f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -302,10 +302,3 @@ void sdram_initialize(struct pei_data *pei_data) if (pei_data->boot_mode != 2) save_mrc_data(pei_data); } - -unsigned long get_top_of_ram(void) -{ - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; -} |