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authorAngel Pons <th3fanbus@gmail.com>2020-03-17 23:09:16 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-03-20 18:11:46 +0000
commit064c7999ae5bab4a29d4ee299f6a8c6a97a5da66 (patch)
tree004529d0b20a9d0281eea4b3bef96b0ba02b7784 /src/northbridge/intel/sandybridge
parent903d9a225e3e0b03824daf6718936851c51e0664 (diff)
downloadcoreboot-064c7999ae5bab4a29d4ee299f6a8c6a97a5da66.tar.xz
nb/intel/sandybridge: Deduplicate report_memory_config
Use the version from native raminit, as it takes the reference clock into account. Change-Id: I00e979bec236167d22561e3eb44b30b4a34ad663 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39622 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
-rw-r--r--src/northbridge/intel/sandybridge/Makefile.inc1
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c50
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c47
-rw-r--r--src/northbridge/intel/sandybridge/raminit_shared.c68
-rw-r--r--src/northbridge/intel/sandybridge/sandybridge.h1
5 files changed, 70 insertions, 97 deletions
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 5fb9fdbc9a..7718bf9acd 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -29,6 +29,7 @@ ramstage-y += common.c
romstage-y += common.c
smm-y += common.c
+romstage-y += raminit_shared.c
ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
romstage-y += early_dmi.c
romstage-y += raminit.c
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index ca78eb3a64..34fb499599 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -38,13 +38,6 @@
/* FIXME: no ECC support */
/* FIXME: no support for 3-channel chipsets */
-static const char *ecc_decoder[] = {
- "inactive",
- "active on IO",
- "disabled on IO",
- "active",
-};
-
static void wait_txt_clear(void)
{
struct cpuid_result cp = cpuid_ext(1, 0);
@@ -90,49 +83,6 @@ static void fill_smbios17(ramctr_timing *ctrl)
}
}
-#define ON_OFF(val) (((val) & 1) ? "on" : "off")
-
-/* Print the memory controller configuration as read from the memory controller registers. */
-static void report_memory_config(void)
-{
- u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS];
- int i;
-
- addr_decoder_common = MCHBAR32(MAD_CHNL);
- addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0);
- addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
-
- const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
-
- printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk);
- printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
- (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100);
-
- printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
- (addr_decoder_common >> 0) & 3,
- (addr_decoder_common >> 2) & 3,
- (addr_decoder_common >> 4) & 3);
-
- for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
- u32 ch_conf = addr_decode_ch[i];
- printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
- printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
- printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22));
- printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21));
- printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n",
- ((ch_conf >> 0) & 0xff) * 256,
- ((ch_conf >> 19) & 1) ? 16 : 8,
- ((ch_conf >> 17) & 1) ? "dual" : "single",
- ((ch_conf >> 16) & 1) ? "" : ", selected");
- printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n",
- ((ch_conf >> 8) & 0xff) * 256,
- ((ch_conf >> 20) & 1) ? 16 : 8,
- ((ch_conf >> 18) & 1) ? "dual" : "single",
- ((ch_conf >> 16) & 1) ? ", selected" : "");
- }
-}
-#undef ON_OFF
-
/* Return CRC16 match for all SPDs */
static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
{
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 5b4b46c583..6d00afa6cb 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -126,53 +126,6 @@ static void prepare_mrc_cache(struct pei_data *pei_data)
pei_data->mrc_input_len);
}
-static const char *ecc_decoder[] = {
- "inactive",
- "active on IO",
- "disabled on IO",
- "active",
-};
-
-#define ON_OFF(val) (((val) & 1) ? "on" : "off")
-
-/* Print the memory controller configuration as read from the memory controller registers. */
-static void report_memory_config(void)
-{
- u32 addr_decoder_common, addr_decode_ch[2];
- int i;
-
- addr_decoder_common = MCHBAR32(MAD_CHNL);
- addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0);
- addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
-
- printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
- (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
-
- printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
- (addr_decoder_common >> 0) & 3,
- (addr_decoder_common >> 2) & 3,
- (addr_decoder_common >> 4) & 3);
-
- for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
- u32 ch_conf = addr_decode_ch[i];
- printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
- printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
- printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22));
- printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21));
- printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n",
- ((ch_conf >> 0) & 0xff) * 256,
- ((ch_conf >> 19) & 1) ? 16 : 8,
- ((ch_conf >> 17) & 1) ? "dual" : "single",
- ((ch_conf >> 16) & 1) ? "" : ", selected");
- printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n",
- ((ch_conf >> 8) & 0xff) * 256,
- ((ch_conf >> 20) & 1) ? 16 : 8,
- ((ch_conf >> 18) & 1) ? "dual" : "single",
- ((ch_conf >> 16) & 1) ? ", selected" : "");
- }
-}
-#undef ON_OFF
-
/**
* Find PEI executable in coreboot filesystem and execute it.
*
diff --git a/src/northbridge/intel/sandybridge/raminit_shared.c b/src/northbridge/intel/sandybridge/raminit_shared.c
new file mode 100644
index 0000000000..6162544bdc
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/raminit_shared.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <types.h>
+
+#include "sandybridge.h"
+
+static const char *const ecc_decoder[] = {
+ "inactive",
+ "active on IO",
+ "disabled on IO",
+ "active",
+};
+
+#define ON_OFF(val) (((val) & 1) ? "on" : "off")
+
+/* Print the memory controller configuration as read from the memory controller registers. */
+void report_memory_config(void)
+{
+ u32 addr_decoder_common, addr_decode_ch[2];
+ int i;
+
+ addr_decoder_common = MCHBAR32(MAD_CHNL);
+ addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0);
+ addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
+
+ const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
+
+ printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk);
+ printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
+ (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100);
+
+ printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
+ (addr_decoder_common >> 0) & 3,
+ (addr_decoder_common >> 2) & 3,
+ (addr_decoder_common >> 4) & 3);
+
+ for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
+ u32 ch_conf = addr_decode_ch[i];
+ printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
+ printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
+ printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22));
+ printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21));
+ printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n",
+ ((ch_conf >> 0) & 0xff) * 256,
+ ((ch_conf >> 19) & 1) ? 16 : 8,
+ ((ch_conf >> 17) & 1) ? "dual" : "single",
+ ((ch_conf >> 16) & 1) ? "" : ", selected");
+ printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n",
+ ((ch_conf >> 8) & 0xff) * 256,
+ ((ch_conf >> 20) & 1) ? 16 : 8,
+ ((ch_conf >> 18) & 1) ? "dual" : "single",
+ ((ch_conf >> 16) & 1) ? ", selected" : "");
+ }
+}
+#undef ON_OFF
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 07d790430f..8fb72ccbf8 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -236,6 +236,7 @@ void early_init_dmi(void);
void mainboard_early_init(int s3resume);
int mainboard_should_reset_usb(int s3resume);
void perform_raminit(int s3resume);
+void report_memory_config(void);
enum platform_type get_platform_type(void);
#include <device/device.h>