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authorArthur Heymans <arthur@aheymans.xyz>2019-11-16 20:06:20 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-18 11:47:05 +0000
commit67d59d1756423a96aca5249b59c4e3759b2f3721 (patch)
treece6c93d12c0fa5c14239b18621f0b9be07c79a96 /src/northbridge/intel/sandybridge
parent2b28a160618018b4d7b7930362e1088c2313901b (diff)
downloadcoreboot-67d59d1756423a96aca5249b59c4e3759b2f3721.tar.xz
nb/intel/sandybridge: Configure DCACHE_BSP_STACK_SIZE
The romstage default is to set stack guards at 0x2000 below end of stack. The code is now overwrites some of the stack guards so increase the stack size to a comfortable 0x2800. Change-Id: I91f559383a987241b343e743d11291f2c100f7f5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge')
-rw-r--r--src/northbridge/intel/sandybridge/Kconfig3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 64ce4d82d9..288dd093bf 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -76,6 +76,9 @@ config DCACHE_RAM_BASE
hex
default 0xfefe0000
+config DCACHE_BSP_STACK_SIZE
+ hex
+ default 0x2800
if USE_NATIVE_RAMINIT